int board_early_init_f(void) { #ifdef CONFIG_FSL_SERDES immap_t *immr = (immap_t *)CFG_IMMR; u32 spridr = in_be32(&immr->sysconf.spridr); /* we check only part num, and don't look for CPU revisions */ switch (PARTID_NO_E(spridr)) { case SPR_8377: fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX, FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); break; case SPR_8378: fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX, FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); break; case SPR_8379: fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA, FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); break; default: printf("serdes not configured: unknown CPU part number: " "%04x\n", spridr >> 16); break; } #endif /* CONFIG_FSL_SERDES */ return 0; }
static void setup_serdes(void) { fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX, FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); }
int board_early_init_f(void) { u8 *bcsr = (u8 *)CFG_BCSR; /* Enable flash write */ bcsr[0x9] &= ~0x04; /* Clear all of the interrupt of BCSR */ bcsr[0xe] = 0xff; #ifdef CONFIG_FSL_SERDES immap_t *immr = (immap_t *)CFG_IMMR; u32 spridr = in_be32(&immr->sysconf.spridr); /* we check only part num, and don't look for CPU revisions */ switch (PARTID_NO_E(spridr)) { case SPR_8377: fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX, FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); break; case SPR_8378: fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX, FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); break; case SPR_8379: fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA, FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); break; default: printf("serdes not configured: unknown CPU part number: " "%04x\n", spridr >> 16); break; } #endif /* CONFIG_FSL_SERDES */ return 0; }
void pci_init_board(void) { immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; sysconf83xx_t *sysconf = &immr->sysconf; law83xx_t *pcie_law = sysconf->pcielaw; struct pci_region *pcie_reg[] = { pcie_regions_0 }; fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX, FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); /* Deassert the resets in the control register */ out_be32(&sysconf->pecr1, 0xE0008000); udelay(2000); /* Configure PCI Express Local Access Windows */ out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR); out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB); mpc83xx_pcie_init(1, pcie_reg); }