/******************************************************************************* * Perform the very early platform specific architectural setup here. At the * moment this is only intializes the MMU ******************************************************************************/ void tsp_plat_arch_setup(void) { fvp_configure_mmu_el1(BL32_RO_BASE, (BL32_COHERENT_RAM_LIMIT - BL32_RO_BASE), BL32_RO_BASE, BL32_RO_LIMIT, BL32_COHERENT_RAM_BASE, BL32_COHERENT_RAM_LIMIT); }
/******************************************************************************* * Perform the very early platform specific architectural setup here. At the * moment this is only intializes the MMU ******************************************************************************/ void tsp_plat_arch_setup(void) { fvp_configure_mmu_el1(BL32_RO_BASE, (BL32_END - BL32_RO_BASE), BL32_RO_BASE, BL32_RO_LIMIT #if USE_COHERENT_MEM , BL32_COHERENT_RAM_BASE, BL32_COHERENT_RAM_LIMIT #endif ); }
/******************************************************************************* * Perform the very early platform specific architectural setup here. At the * moment this is only intializes the mmu in a quick and dirty way. ******************************************************************************/ void bl2_plat_arch_setup(void) { fvp_configure_mmu_el1(bl2_tzram_layout.total_base, bl2_tzram_layout.total_size, BL2_RO_BASE, BL2_RO_LIMIT #if USE_COHERENT_MEM , BL2_COHERENT_RAM_BASE, BL2_COHERENT_RAM_LIMIT #endif ); }