/* Support function to determine the return address of the function
'count' frames back up the stack. */
rtx
lm32_return_addr_rtx (int count, rtx frame)
{
rtx r;
if (count == 0)
{
/* *mjs* This test originally used leaf_function_p (), we now use
the regs_ever_live test which I *think* is more accurate. */
if (!df_regs_ever_live_p(RA_REGNUM))
{
r = gen_rtx_REG (Pmode, RA_REGNUM);
}
else
{
r = gen_rtx_MEM (Pmode,
gen_rtx_PLUS (Pmode, frame,
GEN_INT(- 2 * UNITS_PER_WORD)));
set_mem_alias_set (r, get_frame_alias_set ());
}
}
else if (flag_omit_frame_pointer)
r = NULL_RTX;
else
{
r = gen_rtx_MEM (Pmode,
gen_rtx_PLUS (Pmode, frame,
GEN_INT(- 2 * UNITS_PER_WORD)));
set_mem_alias_set (r, get_frame_alias_set ());
}
return r;
}
/* Support function to determine the return address of the function
'count' frames back up the stack. */
rtx
lm32_return_addr_rtx (int count, rtx frame)
{
rtx r;
if (count == 0)
{
if (!df_regs_ever_live_p (RA_REGNUM))
r = gen_rtx_REG (Pmode, RA_REGNUM);
else
{
r = gen_rtx_MEM (Pmode,
gen_rtx_PLUS (Pmode, frame,
GEN_INT (-2 * UNITS_PER_WORD)));
set_mem_alias_set (r, get_frame_alias_set ());
}
}
else if (flag_omit_frame_pointer)
r = NULL_RTX;
else
{
r = gen_rtx_MEM (Pmode,
gen_rtx_PLUS (Pmode, frame,
GEN_INT (-2 * UNITS_PER_WORD)));
set_mem_alias_set (r, get_frame_alias_set ());
}
return r;
}
static void
moxie_setup_incoming_varargs (cumulative_args_t cum_v,
machine_mode mode ATTRIBUTE_UNUSED,
tree type ATTRIBUTE_UNUSED,
int *pretend_size, int no_rtl)
{
CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
int regno;
int regs = 8 - *cum;
*pretend_size = regs < 0 ? 0 : GET_MODE_SIZE (SImode) * regs;
if (no_rtl)
return;
for (regno = *cum; regno < 8; regno++)
{
rtx reg = gen_rtx_REG (SImode, regno);
rtx slot = gen_rtx_PLUS (Pmode,
gen_rtx_REG (SImode, ARG_POINTER_REGNUM),
GEN_INT (UNITS_PER_WORD * (3 + (regno-2))));
emit_move_insn (gen_rtx_MEM (SImode, slot), reg);
}
}
/* Transform (subreg (plus reg const)) to (plus (subreg reg) const)
when it is possible. Return X or the transformation result if the
transformation is done. */
static rtx
move_plus_up (rtx x)
{
rtx subreg_reg;
enum machine_mode x_mode, subreg_reg_mode;
if (GET_CODE (x) != SUBREG || !subreg_lowpart_p (x))
return x;
subreg_reg = SUBREG_REG (x);
x_mode = GET_MODE (x);
subreg_reg_mode = GET_MODE (subreg_reg);
if (GET_CODE (x) == SUBREG && GET_CODE (subreg_reg) == PLUS
&& GET_MODE_SIZE (x_mode) <= GET_MODE_SIZE (subreg_reg_mode)
&& CONSTANT_P (XEXP (subreg_reg, 1))
&& GET_MODE_CLASS (x_mode) == MODE_INT
&& GET_MODE_CLASS (subreg_reg_mode) == MODE_INT)
{
rtx cst = simplify_subreg (x_mode, XEXP (subreg_reg, 1), subreg_reg_mode,
subreg_lowpart_offset (x_mode,
subreg_reg_mode));
if (cst && CONSTANT_P (cst))
return gen_rtx_PLUS (x_mode, lowpart_subreg (x_mode,
XEXP (subreg_reg, 0),
subreg_reg_mode), cst);
}
return x;
}
/* Compute the sum of X and Y, making canonicalizations assumed in an
address, namely: sum constant integers, surround the sum of two
constants with a CONST, put the constant as the second operand, and
group the constant on the outermost sum.
This routine assumes both inputs are already in canonical form. */
static rtx
form_sum (rtx x, rtx y)
{
machine_mode mode = GET_MODE (x);
if (mode == VOIDmode)
mode = GET_MODE (y);
if (mode == VOIDmode)
mode = Pmode;
if (CONST_INT_P (x))
return plus_constant (mode, y, INTVAL (x));
else if (CONST_INT_P (y))
return plus_constant (mode, x, INTVAL (y));
else if (CONSTANT_P (x))
std::swap (x, y);
if (GET_CODE (x) == PLUS && CONSTANT_P (XEXP (x, 1)))
return form_sum (XEXP (x, 0), form_sum (XEXP (x, 1), y));
/* Note that if the operands of Y are specified in the opposite
order in the recursive calls below, infinite recursion will
occur. */
if (GET_CODE (y) == PLUS && CONSTANT_P (XEXP (y, 1)))
return form_sum (form_sum (x, XEXP (y, 0)), XEXP (y, 1));
/* If both constant, encapsulate sum. Otherwise, just form sum. A
constant will have been placed second. */
if (CONSTANT_P (x) && CONSTANT_P (y))
{
if (GET_CODE (x) == CONST)
x = XEXP (x, 0);
if (GET_CODE (y) == CONST)
y = XEXP (y, 0);
return gen_rtx_CONST (VOIDmode, gen_rtx_PLUS (mode, x, y));
}
return gen_rtx_PLUS (mode, x, y);
}
/* Generate and emit RTL to save or restore callee save registers. */
static void
expand_save_restore (struct lm32_frame_info *info, int op)
{
unsigned int reg_save_mask = info->reg_save_mask;
int regno;
HOST_WIDE_INT offset;
rtx insn;
/* Callee saves are below locals and above outgoing arguments. */
offset = info->args_size + info->callee_size;
for (regno = 0; regno <= 31; regno++)
{
if ((reg_save_mask & (1 << regno)) != 0)
{
rtx offset_rtx;
rtx mem;
offset_rtx = GEN_INT (offset);
if (satisfies_constraint_K (offset_rtx))
{
mem = gen_rtx_MEM (word_mode,
gen_rtx_PLUS (Pmode,
stack_pointer_rtx,
offset_rtx));
}
else
{
/* r10 is caller saved so it can be used as a temp reg. */
rtx r10;
r10 = gen_rtx_REG (word_mode, 10);
insn = emit_move_insn (r10, offset_rtx);
if (op == 0)
RTX_FRAME_RELATED_P (insn) = 1;
insn = emit_add (r10, r10, stack_pointer_rtx);
if (op == 0)
RTX_FRAME_RELATED_P (insn) = 1;
mem = gen_rtx_MEM (word_mode, r10);
}
if (op == 0)
insn = emit_move_insn (mem, gen_rtx_REG (word_mode, regno));
else
insn = emit_move_insn (gen_rtx_REG (word_mode, regno), mem);
/* only prologue instructions which set the sp fp or save a
register should be marked as frame related. */
if (op == 0)
RTX_FRAME_RELATED_P (insn) = 1;
offset -= UNITS_PER_WORD;
}
}
}
/* Generate and emit RTL to save or restore callee save registers */
static void
expand_save_restore (struct lm32_frame_info *info, int op)
{
unsigned int reg_save_mask = info->reg_save_mask;
int regno;
HOST_WIDE_INT offset;
rtx insn;
/* Callee saves are below locals and above outgoing arguments */
offset = info->args_size + info->callee_size;
for (regno = 0; regno <= 31; regno++)
{
if ((reg_save_mask & (1 << regno)) != 0)
{
if (op == 0)
{
insn = emit_move_insn (gen_rtx_MEM (word_mode,
gen_rtx_PLUS (Pmode,
stack_pointer_rtx,
GEN_INT (offset))),
gen_rtx_REG (word_mode, regno));
}
else
{
insn = emit_move_insn (gen_rtx_REG (word_mode, regno),
gen_rtx_MEM (word_mode,
gen_rtx_PLUS (Pmode,
stack_pointer_rtx,
GEN_INT (offset))));
}
/* only prologue instructions which set the sp fp or save a
register should be marked as frame related */
if (op==0)
RTX_FRAME_RELATED_P (insn) = 1;
offset -= UNITS_PER_WORD;
}
}
}
static unsigned int arm_pertask_ssp_rtl_execute(void)
{
rtx_insn *insn;
for (insn = get_insns(); insn; insn = NEXT_INSN(insn)) {
const char *sym;
rtx body;
rtx mask, masked_sp;
/*
* Find a SET insn involving a SYMBOL_REF to __stack_chk_guard
*/
if (!INSN_P(insn))
continue;
body = PATTERN(insn);
if (GET_CODE(body) != SET ||
GET_CODE(SET_SRC(body)) != SYMBOL_REF)
continue;
sym = XSTR(SET_SRC(body), 0);
if (strcmp(sym, "__stack_chk_guard"))
continue;
/*
* Replace the source of the SET insn with an expression that
* produces the address of the copy of the stack canary value
* stored in struct thread_info
*/
mask = GEN_INT(sext_hwi(sp_mask, GET_MODE_PRECISION(Pmode)));
masked_sp = gen_reg_rtx(Pmode);
emit_insn_before(gen_rtx_set(masked_sp,
gen_rtx_AND(Pmode,
stack_pointer_rtx,
mask)),
insn);
SET_SRC(body) = gen_rtx_PLUS(Pmode, masked_sp,
GEN_INT(canary_offset));
}
return 0;
}
static void
gen_addr_rtx (enum machine_mode address_mode,
rtx symbol, rtx base, rtx index, rtx step, rtx offset,
rtx *addr, rtx **step_p, rtx **offset_p)
{
rtx act_elem;
*addr = NULL_RTX;
if (step_p)
*step_p = NULL;
if (offset_p)
*offset_p = NULL;
if (index)
{
act_elem = index;
if (step)
{
act_elem = gen_rtx_MULT (address_mode, act_elem, step);
if (step_p)
*step_p = &XEXP (act_elem, 1);
}
*addr = act_elem;
}
if (base && base != const0_rtx)
{
if (*addr)
*addr = simplify_gen_binary (PLUS, address_mode, base, *addr);
else
*addr = base;
}
if (symbol)
{
act_elem = symbol;
if (offset)
{
act_elem = gen_rtx_PLUS (address_mode, act_elem, offset);
if (offset_p)
*offset_p = &XEXP (act_elem, 1);
if (GET_CODE (symbol) == SYMBOL_REF
|| GET_CODE (symbol) == LABEL_REF
|| GET_CODE (symbol) == CONST)
act_elem = gen_rtx_CONST (address_mode, act_elem);
}
if (*addr)
*addr = gen_rtx_PLUS (address_mode, *addr, act_elem);
else
*addr = act_elem;
}
else if (offset)
{
if (*addr)
{
*addr = gen_rtx_PLUS (address_mode, *addr, offset);
if (offset_p)
*offset_p = &XEXP (*addr, 1);
}
else
{
*addr = offset;
if (offset_p)
*offset_p = addr;
}
}
if (!*addr)
*addr = const0_rtx;
}
static void
emit_case_bit_tests (gswitch *swtch, tree index_expr,
tree minval, tree range, tree maxval)
{
struct case_bit_test test[MAX_CASE_BIT_TESTS];
unsigned int i, j, k;
unsigned int count;
basic_block switch_bb = gimple_bb (swtch);
basic_block default_bb, new_default_bb, new_bb;
edge default_edge;
bool update_dom = dom_info_available_p (CDI_DOMINATORS);
vec<basic_block> bbs_to_fix_dom = vNULL;
tree index_type = TREE_TYPE (index_expr);
tree unsigned_index_type = unsigned_type_for (index_type);
unsigned int branch_num = gimple_switch_num_labels (swtch);
gimple_stmt_iterator gsi;
gassign *shift_stmt;
tree idx, tmp, csui;
tree word_type_node = lang_hooks.types.type_for_mode (word_mode, 1);
tree word_mode_zero = fold_convert (word_type_node, integer_zero_node);
tree word_mode_one = fold_convert (word_type_node, integer_one_node);
int prec = TYPE_PRECISION (word_type_node);
wide_int wone = wi::one (prec);
memset (&test, 0, sizeof (test));
/* Get the edge for the default case. */
tmp = gimple_switch_default_label (swtch);
default_bb = label_to_block (CASE_LABEL (tmp));
default_edge = find_edge (switch_bb, default_bb);
/* Go through all case labels, and collect the case labels, profile
counts, and other information we need to build the branch tests. */
count = 0;
for (i = 1; i < branch_num; i++)
{
unsigned int lo, hi;
tree cs = gimple_switch_label (swtch, i);
tree label = CASE_LABEL (cs);
edge e = find_edge (switch_bb, label_to_block (label));
for (k = 0; k < count; k++)
if (e == test[k].target_edge)
break;
if (k == count)
{
gcc_checking_assert (count < MAX_CASE_BIT_TESTS);
test[k].mask = wi::zero (prec);
test[k].target_edge = e;
test[k].label = label;
test[k].bits = 1;
count++;
}
else
test[k].bits++;
lo = tree_to_uhwi (int_const_binop (MINUS_EXPR,
CASE_LOW (cs), minval));
if (CASE_HIGH (cs) == NULL_TREE)
hi = lo;
else
hi = tree_to_uhwi (int_const_binop (MINUS_EXPR,
CASE_HIGH (cs), minval));
for (j = lo; j <= hi; j++)
test[k].mask |= wi::lshift (wone, j);
}
qsort (test, count, sizeof (*test), case_bit_test_cmp);
/* If all values are in the 0 .. BITS_PER_WORD-1 range, we can get rid of
the minval subtractions, but it might make the mask constants more
expensive. So, compare the costs. */
if (compare_tree_int (minval, 0) > 0
&& compare_tree_int (maxval, GET_MODE_BITSIZE (word_mode)) < 0)
{
int cost_diff;
HOST_WIDE_INT m = tree_to_uhwi (minval);
rtx reg = gen_raw_REG (word_mode, 10000);
bool speed_p = optimize_bb_for_speed_p (gimple_bb (swtch));
cost_diff = set_rtx_cost (gen_rtx_PLUS (word_mode, reg,
GEN_INT (-m)), speed_p);
for (i = 0; i < count; i++)
{
rtx r = immed_wide_int_const (test[i].mask, word_mode);
cost_diff += set_src_cost (gen_rtx_AND (word_mode, reg, r),
word_mode, speed_p);
r = immed_wide_int_const (wi::lshift (test[i].mask, m), word_mode);
cost_diff -= set_src_cost (gen_rtx_AND (word_mode, reg, r),
word_mode, speed_p);
}
if (cost_diff > 0)
{
for (i = 0; i < count; i++)
test[i].mask = wi::lshift (test[i].mask, m);
minval = build_zero_cst (TREE_TYPE (minval));
range = maxval;
}
}
/* We generate two jumps to the default case label.
Split the default edge, so that we don't have to do any PHI node
updating. */
new_default_bb = split_edge (default_edge);
if (update_dom)
{
bbs_to_fix_dom.create (10);
bbs_to_fix_dom.quick_push (switch_bb);
bbs_to_fix_dom.quick_push (default_bb);
bbs_to_fix_dom.quick_push (new_default_bb);
}
/* Now build the test-and-branch code. */
gsi = gsi_last_bb (switch_bb);
/* idx = (unsigned)x - minval. */
idx = fold_convert (unsigned_index_type, index_expr);
idx = fold_build2 (MINUS_EXPR, unsigned_index_type, idx,
fold_convert (unsigned_index_type, minval));
idx = force_gimple_operand_gsi (&gsi, idx,
/*simple=*/true, NULL_TREE,
/*before=*/true, GSI_SAME_STMT);
/* if (idx > range) goto default */
range = force_gimple_operand_gsi (&gsi,
fold_convert (unsigned_index_type, range),
/*simple=*/true, NULL_TREE,
/*before=*/true, GSI_SAME_STMT);
tmp = fold_build2 (GT_EXPR, boolean_type_node, idx, range);
new_bb = hoist_edge_and_branch_if_true (&gsi, tmp, default_edge, update_dom);
if (update_dom)
bbs_to_fix_dom.quick_push (new_bb);
gcc_assert (gimple_bb (swtch) == new_bb);
gsi = gsi_last_bb (new_bb);
/* Any blocks dominated by the GIMPLE_SWITCH, but that are not successors
of NEW_BB, are still immediately dominated by SWITCH_BB. Make it so. */
if (update_dom)
{
vec<basic_block> dom_bbs;
basic_block dom_son;
dom_bbs = get_dominated_by (CDI_DOMINATORS, new_bb);
FOR_EACH_VEC_ELT (dom_bbs, i, dom_son)
{
edge e = find_edge (new_bb, dom_son);
if (e && single_pred_p (e->dest))
continue;
set_immediate_dominator (CDI_DOMINATORS, dom_son, switch_bb);
bbs_to_fix_dom.safe_push (dom_son);
}
dom_bbs.release ();
}
void
init_caller_save ()
{
char *first_obj = (char *) oballoc (0);
rtx addr_reg;
int offset;
rtx address;
int i, j;
/* First find all the registers that we need to deal with and all
the modes that they can have. If we can't find a mode to use,
we can't have the register live over calls. */
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
{
if (call_used_regs[i] && ! call_fixed_regs[i])
{
for (j = 1; j <= MOVE_MAX / UNITS_PER_WORD; j++)
{
regno_save_mode[i][j] = choose_hard_reg_mode (i, j);
if (regno_save_mode[i][j] == VOIDmode && j == 1)
{
call_fixed_regs[i] = 1;
SET_HARD_REG_BIT (call_fixed_reg_set, i);
}
}
}
else
regno_save_mode[i][1] = VOIDmode;
}
/* The following code tries to approximate the conditions under which
we can easily save and restore a register without scratch registers or
other complexities. It will usually work, except under conditions where
the validity of an insn operand is dependent on the address offset.
No such cases are currently known.
We first find a typical offset from some BASE_REG_CLASS register.
This address is chosen by finding the first register in the class
and by finding the smallest power of two that is a valid offset from
that register in every mode we will use to save registers. */
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
if (TEST_HARD_REG_BIT (reg_class_contents[(int) BASE_REG_CLASS], i))
break;
if (i == FIRST_PSEUDO_REGISTER)
abort ();
addr_reg = gen_rtx_REG (Pmode, i);
for (offset = 1 << (HOST_BITS_PER_INT / 2); offset; offset >>= 1)
{
address = gen_rtx_PLUS (Pmode, addr_reg, GEN_INT (offset));
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
if (regno_save_mode[i][1] != VOIDmode
&& ! strict_memory_address_p (regno_save_mode[i][1], address))
break;
if (i == FIRST_PSEUDO_REGISTER)
break;
}
/* If we didn't find a valid address, we must use register indirect. */
if (offset == 0)
address = addr_reg;
/* Next we try to form an insn to save and restore the register. We
see if such an insn is recognized and meets its constraints. */
start_sequence ();
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
for (j = 1; j <= MOVE_MAX / UNITS_PER_WORD; j++)
if (regno_save_mode[i][j] != VOIDmode)
{
rtx mem = gen_rtx_MEM (regno_save_mode[i][j], address);
rtx reg = gen_rtx_REG (regno_save_mode[i][j], i);
rtx savepat = gen_rtx_SET (VOIDmode, mem, reg);
rtx restpat = gen_rtx_SET (VOIDmode, reg, mem);
rtx saveinsn = emit_insn (savepat);
rtx restinsn = emit_insn (restpat);
int ok;
reg_save_code[i][j] = recog_memoized (saveinsn);
reg_restore_code[i][j] = recog_memoized (restinsn);
/* Now extract both insns and see if we can meet their
constraints. */
ok = (reg_save_code[i][j] != -1 && reg_restore_code[i][j] != -1);
if (ok)
{
insn_extract (saveinsn);
ok = constrain_operands (reg_save_code[i][j], 1);
insn_extract (restinsn);
ok &= constrain_operands (reg_restore_code[i][j], 1);
}
if (! ok)
{
regno_save_mode[i][j] = VOIDmode;
if (j == 1)
{
call_fixed_regs[i] = 1;
SET_HARD_REG_BIT (call_fixed_reg_set, i);
}
}
}
end_sequence ();
obfree (first_obj);
}
static bool
try_merge (void)
{
enum gen_form gen_form;
rtx mem = *mem_insn.mem_loc;
rtx inc_reg = inc_insn.form == FORM_POST_ADD ?
inc_insn.reg_res : mem_insn.reg0;
/* The width of the mem being accessed. */
int size = GET_MODE_SIZE (GET_MODE (mem));
rtx last_insn = NULL;
enum machine_mode reg_mode = GET_MODE (inc_reg);
switch (inc_insn.form)
{
case FORM_PRE_ADD:
case FORM_PRE_INC:
last_insn = mem_insn.insn;
break;
case FORM_POST_INC:
case FORM_POST_ADD:
last_insn = inc_insn.insn;
break;
case FORM_last:
default:
gcc_unreachable ();
}
/* Cannot handle auto inc of the stack. */
if (inc_reg == stack_pointer_rtx)
{
if (dump_file)
fprintf (dump_file, "cannot inc stack %d failure\n", REGNO (inc_reg));
return false;
}
/* Look to see if the inc register is dead after the memory
reference. If it is, do not do the combination. */
if (find_regno_note (last_insn, REG_DEAD, REGNO (inc_reg)))
{
if (dump_file)
fprintf (dump_file, "dead failure %d\n", REGNO (inc_reg));
return false;
}
mem_insn.reg1_state = (mem_insn.reg1_is_const)
? set_inc_state (mem_insn.reg1_val, size) : INC_REG;
inc_insn.reg1_state = (inc_insn.reg1_is_const)
? set_inc_state (inc_insn.reg1_val, size) : INC_REG;
/* Now get the form that we are generating. */
gen_form = decision_table
[inc_insn.reg1_state][mem_insn.reg1_state][inc_insn.form];
if (dbg_cnt (auto_inc_dec) == false)
return false;
switch (gen_form)
{
default:
case NOTHING:
return false;
case SIMPLE_PRE_INC: /* ++size */
if (dump_file)
fprintf (dump_file, "trying SIMPLE_PRE_INC\n");
return attempt_change (gen_rtx_PRE_INC (reg_mode, inc_reg), inc_reg);
break;
case SIMPLE_POST_INC: /* size++ */
if (dump_file)
fprintf (dump_file, "trying SIMPLE_POST_INC\n");
return attempt_change (gen_rtx_POST_INC (reg_mode, inc_reg), inc_reg);
break;
case SIMPLE_PRE_DEC: /* --size */
if (dump_file)
fprintf (dump_file, "trying SIMPLE_PRE_DEC\n");
return attempt_change (gen_rtx_PRE_DEC (reg_mode, inc_reg), inc_reg);
break;
case SIMPLE_POST_DEC: /* size-- */
if (dump_file)
fprintf (dump_file, "trying SIMPLE_POST_DEC\n");
return attempt_change (gen_rtx_POST_DEC (reg_mode, inc_reg), inc_reg);
break;
case DISP_PRE: /* ++con */
if (dump_file)
fprintf (dump_file, "trying DISP_PRE\n");
return attempt_change (gen_rtx_PRE_MODIFY (reg_mode,
inc_reg,
gen_rtx_PLUS (reg_mode,
inc_reg,
inc_insn.reg1)),
inc_reg);
break;
case DISP_POST: /* con++ */
if (dump_file)
fprintf (dump_file, "trying POST_DISP\n");
return attempt_change (gen_rtx_POST_MODIFY (reg_mode,
inc_reg,
gen_rtx_PLUS (reg_mode,
inc_reg,
inc_insn.reg1)),
inc_reg);
break;
case REG_PRE: /* ++reg */
if (dump_file)
fprintf (dump_file, "trying PRE_REG\n");
return attempt_change (gen_rtx_PRE_MODIFY (reg_mode,
inc_reg,
gen_rtx_PLUS (reg_mode,
inc_reg,
inc_insn.reg1)),
inc_reg);
break;
case REG_POST: /* reg++ */
if (dump_file)
fprintf (dump_file, "trying POST_REG\n");
return attempt_change (gen_rtx_POST_MODIFY (reg_mode,
inc_reg,
gen_rtx_PLUS (reg_mode,
inc_reg,
inc_insn.reg1)),
inc_reg);
break;
}
}
/* Scan X and replace any eliminable registers (such as fp) with a
replacement (such as sp) if SUBST_P, plus an offset. The offset is
a change in the offset between the eliminable register and its
substitution if UPDATE_P, or the full offset if FULL_P, or
otherwise zero. If FULL_P, we also use the SP offsets for
elimination to SP. If UPDATE_P, use UPDATE_SP_OFFSET for updating
offsets of register elimnable to SP. If UPDATE_SP_OFFSET is
non-zero, don't use difference of the offset and the previous
offset.
MEM_MODE is the mode of an enclosing MEM. We need this to know how
much to adjust a register for, e.g., PRE_DEC. Also, if we are
inside a MEM, we are allowed to replace a sum of a hard register
and the constant zero with the hard register, which we cannot do
outside a MEM. In addition, we need to record the fact that a
hard register is referenced outside a MEM.
If we make full substitution to SP for non-null INSN, add the insn
sp offset. */
rtx
lra_eliminate_regs_1 (rtx_insn *insn, rtx x, machine_mode mem_mode,
bool subst_p, bool update_p,
HOST_WIDE_INT update_sp_offset, bool full_p)
{
enum rtx_code code = GET_CODE (x);
struct lra_elim_table *ep;
rtx new_rtx;
int i, j;
const char *fmt;
int copied = 0;
lra_assert (!update_p || !full_p);
lra_assert (update_sp_offset == 0 || (!subst_p && update_p && !full_p));
if (! current_function_decl)
return x;
switch (code)
{
CASE_CONST_ANY:
case CONST:
case SYMBOL_REF:
case CODE_LABEL:
case PC:
case CC0:
case ASM_INPUT:
case ADDR_VEC:
case ADDR_DIFF_VEC:
case RETURN:
return x;
case REG:
/* First handle the case where we encounter a bare hard register
that is eliminable. Replace it with a PLUS. */
if ((ep = get_elimination (x)) != NULL)
{
rtx to = subst_p ? ep->to_rtx : ep->from_rtx;
if (update_sp_offset != 0)
{
if (ep->to_rtx == stack_pointer_rtx)
return plus_constant (Pmode, to, update_sp_offset);
return to;
}
else if (update_p)
return plus_constant (Pmode, to, ep->offset - ep->previous_offset);
else if (full_p)
return plus_constant (Pmode, to,
ep->offset
- (insn != NULL_RTX
&& ep->to_rtx == stack_pointer_rtx
? lra_get_insn_recog_data (insn)->sp_offset
: 0));
else
return to;
}
return x;
case PLUS:
/* If this is the sum of an eliminable register and a constant, rework
the sum. */
if (REG_P (XEXP (x, 0)) && CONSTANT_P (XEXP (x, 1)))
{
if ((ep = get_elimination (XEXP (x, 0))) != NULL)
{
HOST_WIDE_INT offset;
rtx to = subst_p ? ep->to_rtx : ep->from_rtx;
if (! update_p && ! full_p)
return gen_rtx_PLUS (Pmode, to, XEXP (x, 1));
if (update_sp_offset != 0)
offset = ep->to_rtx == stack_pointer_rtx ? update_sp_offset : 0;
else
offset = (update_p
? ep->offset - ep->previous_offset : ep->offset);
if (full_p && insn != NULL_RTX && ep->to_rtx == stack_pointer_rtx)
offset -= lra_get_insn_recog_data (insn)->sp_offset;
if (CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) == -offset)
return to;
else
return gen_rtx_PLUS (Pmode, to,
plus_constant (Pmode,
XEXP (x, 1), offset));
}
/* If the hard register is not eliminable, we are done since
the other operand is a constant. */
return x;
}
/* If this is part of an address, we want to bring any constant
to the outermost PLUS. We will do this by doing hard
register replacement in our operands and seeing if a constant
shows up in one of them.
Note that there is no risk of modifying the structure of the
insn, since we only get called for its operands, thus we are
either modifying the address inside a MEM, or something like
an address operand of a load-address insn. */
{
rtx new0 = lra_eliminate_regs_1 (insn, XEXP (x, 0), mem_mode,
subst_p, update_p,
update_sp_offset, full_p);
rtx new1 = lra_eliminate_regs_1 (insn, XEXP (x, 1), mem_mode,
subst_p, update_p,
update_sp_offset, full_p);
new0 = move_plus_up (new0);
new1 = move_plus_up (new1);
if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
return form_sum (new0, new1);
}
return x;
case MULT:
/* If this is the product of an eliminable hard register and a
constant, apply the distribute law and move the constant out
so that we have (plus (mult ..) ..). This is needed in order
to keep load-address insns valid. This case is pathological.
We ignore the possibility of overflow here. */
if (REG_P (XEXP (x, 0)) && CONST_INT_P (XEXP (x, 1))
&& (ep = get_elimination (XEXP (x, 0))) != NULL)
{
rtx to = subst_p ? ep->to_rtx : ep->from_rtx;
if (update_sp_offset != 0)
{
if (ep->to_rtx == stack_pointer_rtx)
return plus_constant (Pmode,
gen_rtx_MULT (Pmode, to, XEXP (x, 1)),
update_sp_offset * INTVAL (XEXP (x, 1)));
return gen_rtx_MULT (Pmode, to, XEXP (x, 1));
}
else if (update_p)
return plus_constant (Pmode,
gen_rtx_MULT (Pmode, to, XEXP (x, 1)),
(ep->offset - ep->previous_offset)
* INTVAL (XEXP (x, 1)));
else if (full_p)
{
HOST_WIDE_INT offset = ep->offset;
if (insn != NULL_RTX && ep->to_rtx == stack_pointer_rtx)
offset -= lra_get_insn_recog_data (insn)->sp_offset;
return
plus_constant (Pmode,
gen_rtx_MULT (Pmode, to, XEXP (x, 1)),
offset * INTVAL (XEXP (x, 1)));
}
else
return gen_rtx_MULT (Pmode, to, XEXP (x, 1));
}
/* fall through */
case CALL:
case COMPARE:
/* See comments before PLUS about handling MINUS. */
case MINUS:
case DIV: case UDIV:
case MOD: case UMOD:
case AND: case IOR: case XOR:
case ROTATERT: case ROTATE:
case ASHIFTRT: case LSHIFTRT: case ASHIFT:
case NE: case EQ:
case GE: case GT: case GEU: case GTU:
case LE: case LT: case LEU: case LTU:
{
rtx new0 = lra_eliminate_regs_1 (insn, XEXP (x, 0), mem_mode,
subst_p, update_p,
update_sp_offset, full_p);
rtx new1 = XEXP (x, 1)
? lra_eliminate_regs_1 (insn, XEXP (x, 1), mem_mode,
subst_p, update_p,
update_sp_offset, full_p) : 0;
if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
}
return x;
case EXPR_LIST:
/* If we have something in XEXP (x, 0), the usual case,
eliminate it. */
if (XEXP (x, 0))
{
new_rtx = lra_eliminate_regs_1 (insn, XEXP (x, 0), mem_mode,
subst_p, update_p,
update_sp_offset, full_p);
if (new_rtx != XEXP (x, 0))
{
/* If this is a REG_DEAD note, it is not valid anymore.
Using the eliminated version could result in creating a
REG_DEAD note for the stack or frame pointer. */
if (REG_NOTE_KIND (x) == REG_DEAD)
return (XEXP (x, 1)
? lra_eliminate_regs_1 (insn, XEXP (x, 1), mem_mode,
subst_p, update_p,
update_sp_offset, full_p)
: NULL_RTX);
x = alloc_reg_note (REG_NOTE_KIND (x), new_rtx, XEXP (x, 1));
}
}
/* fall through */
case INSN_LIST:
case INT_LIST:
/* Now do eliminations in the rest of the chain. If this was
an EXPR_LIST, this might result in allocating more memory than is
strictly needed, but it simplifies the code. */
if (XEXP (x, 1))
{
new_rtx = lra_eliminate_regs_1 (insn, XEXP (x, 1), mem_mode,
subst_p, update_p,
update_sp_offset, full_p);
if (new_rtx != XEXP (x, 1))
return
gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x),
XEXP (x, 0), new_rtx);
}
return x;
case PRE_INC:
case POST_INC:
case PRE_DEC:
case POST_DEC:
/* We do not support elimination of a register that is modified.
elimination_effects has already make sure that this does not
happen. */
return x;
case PRE_MODIFY:
case POST_MODIFY:
/* We do not support elimination of a hard register that is
modified. LRA has already make sure that this does not
happen. The only remaining case we need to consider here is
that the increment value may be an eliminable register. */
if (GET_CODE (XEXP (x, 1)) == PLUS
&& XEXP (XEXP (x, 1), 0) == XEXP (x, 0))
{
rtx new_rtx = lra_eliminate_regs_1 (insn, XEXP (XEXP (x, 1), 1),
mem_mode, subst_p, update_p,
update_sp_offset, full_p);
if (new_rtx != XEXP (XEXP (x, 1), 1))
return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0),
gen_rtx_PLUS (GET_MODE (x),
XEXP (x, 0), new_rtx));
}
return x;
case STRICT_LOW_PART:
case NEG: case NOT:
case SIGN_EXTEND: case ZERO_EXTEND:
case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
case FLOAT: case FIX:
case UNSIGNED_FIX: case UNSIGNED_FLOAT:
case ABS:
case SQRT:
case FFS:
case CLZ:
case CTZ:
case POPCOUNT:
case PARITY:
case BSWAP:
new_rtx = lra_eliminate_regs_1 (insn, XEXP (x, 0), mem_mode,
subst_p, update_p,
update_sp_offset, full_p);
if (new_rtx != XEXP (x, 0))
return gen_rtx_fmt_e (code, GET_MODE (x), new_rtx);
return x;
case SUBREG:
new_rtx = lra_eliminate_regs_1 (insn, SUBREG_REG (x), mem_mode,
subst_p, update_p,
update_sp_offset, full_p);
if (new_rtx != SUBREG_REG (x))
{
int x_size = GET_MODE_SIZE (GET_MODE (x));
int new_size = GET_MODE_SIZE (GET_MODE (new_rtx));
if (MEM_P (new_rtx) && x_size <= new_size)
{
SUBREG_REG (x) = new_rtx;
alter_subreg (&x, false);
return x;
}
else if (! subst_p)
{
/* LRA can transform subregs itself. So don't call
simplify_gen_subreg until LRA transformations are
finished. Function simplify_gen_subreg can do
non-trivial transformations (like truncation) which
might make LRA work to fail. */
SUBREG_REG (x) = new_rtx;
return x;
}
else
return simplify_gen_subreg (GET_MODE (x), new_rtx,
GET_MODE (new_rtx), SUBREG_BYTE (x));
}
return x;
case MEM:
/* Our only special processing is to pass the mode of the MEM to our
recursive call and copy the flags. While we are here, handle this
case more efficiently. */
return
replace_equiv_address_nv
(x,
lra_eliminate_regs_1 (insn, XEXP (x, 0), GET_MODE (x),
subst_p, update_p, update_sp_offset, full_p));
case USE:
/* Handle insn_list USE that a call to a pure function may generate. */
new_rtx = lra_eliminate_regs_1 (insn, XEXP (x, 0), VOIDmode,
subst_p, update_p, update_sp_offset, full_p);
if (new_rtx != XEXP (x, 0))
return gen_rtx_USE (GET_MODE (x), new_rtx);
return x;
case CLOBBER:
case SET:
gcc_unreachable ();
default:
break;
}
/* Process each of our operands recursively. If any have changed, make a
copy of the rtx. */
fmt = GET_RTX_FORMAT (code);
for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
{
if (*fmt == 'e')
{
new_rtx = lra_eliminate_regs_1 (insn, XEXP (x, i), mem_mode,
subst_p, update_p,
update_sp_offset, full_p);
if (new_rtx != XEXP (x, i) && ! copied)
{
x = shallow_copy_rtx (x);
copied = 1;
}
XEXP (x, i) = new_rtx;
}
else if (*fmt == 'E')
{
int copied_vec = 0;
for (j = 0; j < XVECLEN (x, i); j++)
{
new_rtx = lra_eliminate_regs_1 (insn, XVECEXP (x, i, j), mem_mode,
subst_p, update_p,
update_sp_offset, full_p);
if (new_rtx != XVECEXP (x, i, j) && ! copied_vec)
{
rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
XVEC (x, i)->elem);
if (! copied)
{
x = shallow_copy_rtx (x);
copied = 1;
}
XVEC (x, i) = new_v;
copied_vec = 1;
}
XVECEXP (x, i, j) = new_rtx;
}
}
}
return x;
}
