/* Implements both ID and WB */
void do_id_wb_stages()
{
/* Set up write backs. Don't occur until end of cycle */
wb_destE = gen_w_dstE();
wb_valE = gen_w_valE();
wb_destM = gen_w_dstM();
wb_valM = gen_w_valM();
id_ex_next->srca = gen_new_E_srcA();
id_ex_next->srcb = gen_new_E_srcB();
id_ex_next->deste = gen_new_E_dstE();
id_ex_next->destm = gen_new_E_dstM();
/* Read the registers */
d_regvala = get_reg_val(reg, id_ex_next->srca);
d_regvalb = get_reg_val(reg, id_ex_next->srcb);
/* Do forwarding and valA selection */
id_ex_next->vala = gen_new_E_valA();
id_ex_next->valb = gen_new_E_valB();
id_ex_next->icode = if_id_curr->icode;
id_ex_next->ifun = if_id_curr->ifun;
id_ex_next->valc = if_id_curr->valc;
id_ex_next->stage_pc = if_id_curr->stage_pc;
id_ex_next->exception = (if_id_curr->icode == I_HALT) ?
EXC_HALT : if_id_curr->exception;
sim_log("Decode: instr = %s, exc=%s\n",
iname(HPACK(if_id_curr->icode, if_id_curr->ifun)),
exc_name(if_id_curr->exception));
}
/* Implements both ID and WB */
void do_id_wb_stages()
{
/* Set up write backs. Don't occur until end of cycle */
wb_destE = gen_w_dstE();
wb_valE = gen_w_valE();
wb_destM = gen_w_dstM();
wb_valM = gen_w_valM();
/* Update processor status */
status = gen_Stat();
id_ex_next->srca = gen_d_srcA();
id_ex_next->srcb = gen_d_srcB();
id_ex_next->deste = gen_d_dstE();
id_ex_next->destm = gen_d_dstM();
/* Read the registers */
d_regvala = get_reg_val(reg, id_ex_next->srca);
d_regvalb = get_reg_val(reg, id_ex_next->srcb);
/* Do forwarding and valA selection */
id_ex_next->vala = gen_d_valA();
id_ex_next->valb = gen_d_valB();
id_ex_next->icode = if_id_curr->icode;
id_ex_next->ifun = if_id_curr->ifun;
id_ex_next->valc = if_id_curr->valc;
id_ex_next->stage_pc = if_id_curr->stage_pc;
id_ex_next->status = if_id_curr->status;
}
