const bool V3Ntk::reportMultipleDrivenNet(const V3GateType& type, const V3NetId& id) const { assert (type < V3_GATE_TOTAL); assert (validNetId(id)); if (V3_PI != getGateType(id)) Msg(MSG_ERR) << "Multiple-Driven @ " << id.id << "(" << V3GateTypeStr[type] << ")" << ", Exist " << V3GateTypeStr[getGateType(id)] << endl; else if (_globalClk.id == id.id) Msg(MSG_ERR) << "Clock Signal \"" << _globalClk.id << "\" Cannot be Driven, found @ " << id.id << "(" << V3GateTypeStr[type] << ")" << endl; else return false; return true; }
// Ntk Reconstruction Functions void V3Ntk::replaceFanin(const V3RepIdHash& repIdHash) { //cerr << "called replaceFanin" << endl; assert (repIdHash.size()); uint32_t i, inSize; V3GateType type; V3RepIdHash::const_iterator it; for (V3NetId id = V3NetId::makeNetId(1); id.id < _inputData.size(); ++id.id) { type = getGateType(id); if (V3_MODULE == type) { V3NtkModule* const module = getModule(_inputData[id.id][0].value); assert (module); for (i = 0; i < module->getInputList().size(); ++i) { it = repIdHash.find(module->getInputList()[i].id); if (repIdHash.end() == it) continue; module->updateInput(i, module->getInputList()[i].cp ? ~(it->second) : it->second); } } else { inSize = (AIG_NODE == type || isV3PairType(type)) ? 2 : (BV_MUX == type) ? 3 : (V3_FF == type || BV_SLICE == type || isV3ReducedType(type)) ? 1 : 0; for (i = 0; i < inSize; ++i) { it = repIdHash.find(_inputData[id.id][i].id.id); if (repIdHash.end() == it) continue; //cout << "replacing : " << id.id << "'s input\n"; _inputData[id.id][i] = V3NetType(_inputData[id.id][i].id.cp ? ~(it->second) : it->second); } } } }
// put fanins of a net (id) into a vector (nets) in topological order void V3Ntk::dfsOrder(const V3NetId& id, V3NetVec& nets) { if (isLatestMiscData(id)) return; // Set Latest Misc Data setLatestMiscData(id); // Traverse Fanin Logics const V3GateType type = getGateType(id); if(type == AIG_NODE) { dfsOrder(getInputNetId(id, 0), nets); dfsOrder(getInputNetId(id, 1), nets); } nets.push_back(id); // Record Order }
const bool V3Ntk::setBddOrder(V3NtkHandler* const handler, const bool& file) const { unsigned supportSize = getInputSize() + getInoutSize() + 2*getLatchSize(); if(supportSize >= bddMgrV->getNumSupports()) { Msg(MSG_ERR) << "BDD Support Size is Smaller Than Current Design Required !!" << endl; return false; } // build support unsigned supportId = 1; for(unsigned i = 0, n = getInputSize(); i < n; ++i) { const V3NetId& nId = (file)? getInput(i) : getInput(n-i-1); bddMgrV->addBddNodeV(nId.id, bddMgrV->getSupport(supportId)()); bddMgrV->addBddNodeV(handler->getNetNameOrFormedWithId(nId), bddMgrV->getSupport(supportId)()); ++supportId; } for(unsigned i = 0, n = getInoutSize(); i < n; ++i) { const V3NetId& nId = (file)? getInout(i) : getInout(n-i-1); bddMgrV->addBddNodeV(nId.id, bddMgrV->getSupport(supportId)()); bddMgrV->addBddNodeV(handler->getNetNameOrFormedWithId(nId), bddMgrV->getSupport(supportId)()); ++supportId; } for(unsigned i = 0, n = getLatchSize(); i < n; ++i) { const V3NetId& nId = (file)? getLatch(i) : getLatch(n-i-1); bddMgrV->addBddNodeV(nId.id, bddMgrV->getSupport(supportId)()); bddMgrV->addBddNodeV(handler->getNetNameOrFormedWithId(nId), bddMgrV->getSupport(supportId)()); ++supportId; } // Next State for(unsigned i = 0, n = getLatchSize(); i < n; ++i) { const V3NetId& nId = (file)? getLatch(i) : getLatch(n-i-1); bddMgrV->addBddNodeV(handler->getNetNameOrFormedWithId(nId)+"_ns", bddMgrV->getSupport(supportId)()); ++supportId; } // Constants for (uint32_t i = 0; i < getConstSize(); ++i) { assert(getGateType(getConst(i)) == AIG_FALSE); bddMgrV->addBddNodeV(getConst(i).id, BddNodeV::_zero()); } return true; }
void V3Ntk::buildBdd(const V3NetId& netId) { V3NetVec orderedNets; orderedNets.clear(); orderedNets.reserve(getNetSize()); newMiscData(); dfsOrder(netId, orderedNets); assert (orderedNets.size() <= getNetSize()); // TODO: build BDD for the specified net here for(unsigned i=0;i<orderedNets.size();i++){ V3NetId& netid= orderedNets[i]; BddNodeV b = bddMgrV->getBddNodeV(netid.id); /* if(!bddMgrV->addBddNodeV(netid.id,b())){ continue; }*/ //cout<<"id:"<<netid.id<<" cp:"<<netid.cp<<endl; //cout<<"type:"<<V3GateTypeStr[getGateType(netid)]<<endl; //cout<<"inputnetsize:"<<getInputNetSize(netid)<<endl; //BddNodeV b = bddMgrV->getBddNodeV(netid.id); if( getGateType(netid)==AIG_NODE ){ assert(getInputNetSize(netid)==2); V3NetId in1=getInputNetId(netid, 0); BddNodeV b1 = bddMgrV->getBddNodeV(in1.id); V3NetId in2=getInputNetId(netid, 1); BddNodeV b2 = bddMgrV->getBddNodeV(in2.id); //cout<<"input:"<<endl; //cout<<in1.id<<" "<<in1.cp<<endl; //cout<<in2.id<<" "<<in2.cp<<endl; /* if (b1() == 0){ buildBdd(in1); } if (b2() == 0){ buildBdd(in2); }*/ if(in1.cp){ b1= ~b1; } if(in2.cp){ b2= ~b2; } b = b1& b2; } else if(getGateType(netid)==V3_FF) { V3NetId in1=getInputNetId(netid, 0); BddNodeV b1 = bddMgrV->getBddNodeV(in1.id); // cout<<"input:"<<endl; // cout<<"input_type:"<<V3GateTypeStr[getGateType(in1)]<<endl; // cout<<in1.id<<" "<<in1.cp<<endl; /* if (b1() == 0){ buildBdd(in1); }*/ if(in1.cp){ // b1= ~b1; } // b = b1;//BddNodeV::_zero; } if(netid.cp){ // b=~b; } bddMgrV->addBddNodeV(netid.id,b()); // cout<<"bdd:"<<b<<endl; } }
void V3Ntk::createClock(const V3NetId& id) { assert (validNetId(id)); assert (V3_PI == getGateType(id)); assert (V3NetUD == _globalClk); _globalClk = id; }
// Ntk Reconstruction Functions void V3BvNtk::resetNetWidth(const V3NetId& id, const uint32_t& width) { assert (validNetId(id)); assert (V3_PI == getGateType(id)); assert (width); _netWidth[id.id] = width; }
const uint32_t V3BvNtk::getInputSliceBit(const V3NetId& id, const bool& msb) const { assert (validNetId(id)); assert (BV_SLICE == getGateType(id)); const V3BusId busId = _inputData[id.id][1].value; assert (busId < _V3BusIdVec.size()); return msb ? _V3BusIdVec[busId].bus[0] : _V3BusIdVec[busId].bus[1]; }
const V3BitVecX V3BvNtk::getInputConstValue(const V3NetId& id) const { assert (validNetId(id)); assert (BV_CONST == getGateType(id)); return id.cp ? ~getConstValue(_inputData[id.id][0].value) : getConstValue(_inputData[id.id][0].value); }