//---
const std::vector<std::string>& Processor::getGateKeeperContexts() const
{
// Can't set the table names in constructor, since don't know parent at that time ...
// ... instead, have to set tables names first time this method is called
if( mGateKeeperTables.empty() )
{
mGateKeeperTables.push_back(getPath());
std::string basePath = getPath();
basePath.resize(basePath.size() - getId().size());
mGateKeeperTables.push_back(basePath + getStub().role);
mGateKeeperTables.push_back(basePath + "processors");
mGateKeeperTables.push_back(basePath + getStub().hwtype);
}
return mGateKeeperTables;
}
DummyProcessor::DummyProcessor(const swatch::core::AbstractStub& aStub) :
Processor(aStub),
mDriver(new DummyProcDriver())
{
// 1) Interfaces
registerInterface( new DummyTTC(*mDriver) );
registerInterface( new DummyReadoutInterface(*mDriver) );
registerInterface( new DummyAlgo(*mDriver) );
registerInterface( new processor::InputPortCollection() );
registerInterface( new processor::OutputPortCollection() );
const processor::ProcessorStub& stub = getStub();
for(auto it = stub.rxPorts.begin(); it != stub.rxPorts.end(); it++)
getInputPorts().addPort(new DummyRxPort(it->id, it->number, *mDriver));
for(auto it = stub.txPorts.begin(); it != stub.txPorts.end(); it++)
getOutputPorts().addPort(new DummyTxPort(it->id, it->number, *mDriver));
// 2) Commands
core::Command& reboot = registerCommand<DummyResetCommand>("reboot");
core::Command& reset = registerCommand<DummyResetCommand>("reset");
core::Command& cfgTx = registerCommand<DummyConfigureTxCommand>("configureTx");
core::Command& cfgRx = registerCommand<DummyConfigureRxCommand>("configureRx");
core::Command& cfgDaq = registerCommand<DummyConfigureDaqCommand>("configureDaq");
core::Command& cfgAlgo = registerCommand<DummyConfigureAlgoCommand>("configureAlgo");
registerCommand<DummyProcessorForceClkTtcStateCommand>("forceClkTtcState");
registerCommand<DummyProcessorForceRxPortsStateCommand>("forceRxPortsState");
registerCommand<DummyProcessorForceTxPortsStateCommand>("forceTxPortsState");
registerCommand<DummyProcessorForceReadoutStateCommand>("forceReadoutState");
registerCommand<DummyProcessorForceAlgoStateCommand>("forceAlgoState");
// 3) Command sequences
core::CommandSequence& cfgSeq = registerSequence("configPartA", reset).then(cfgDaq).then(cfgTx);
registerSequence("fullReconfigure", reset).then(cfgDaq).then(cfgAlgo).then(cfgRx).then(cfgTx);
// 4) State machines
processor::RunControlFSM& lFSM = getRunControlFSM();
lFSM.coldReset.add(reboot);
lFSM.setup.add(cfgSeq);
lFSM.configure.add(cfgAlgo);
lFSM.align.add(cfgRx);
lFSM.fsm.addTransition("dummyNoOp", processor::RunControlFSM::kStateAligned, processor::RunControlFSM::kStateInitial);
}
void
be_attribute::GenerateImpureRequestCall(be_ClientImplementation& source)
{
be_AttStubGenerator getStub
(
enclosingScope,
getOpKey,
LocalName (),
GetSignature (AT_Implementation, InterfaceBasename (), pbfalse),
fieldType,
FALSE
);
getStub.Generate(source);
if (!readonly())
{
DDS_StdString setArg ("_nval_");
DDS_StdString setSignature = SetSignature
(
AT_Implementation,
InterfaceBasename(),
FALSE,
setArg
);
be_AttStubGenerator setStub
(
enclosingScope,
setOpKey,
LocalName(),
setSignature,
fieldType,
pbtrue
);
setStub.Generate(source);
}
}
