BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AAS(bxInstruction_c *i)
{
int tmpCF = 0, tmpAF = 0;
/* AAS affects the following flags: A,C */
if (((AL & 0x0F) > 0x09) || get_AF())
{
AX = AX - 0x106;
tmpAF = tmpCF = 1;
}
AL = AL & 0x0f;
/* AAS affects also the following flags: Z,S,O,P */
/* modification of the flags is undocumented */
/* The following behaviour seems to match the P6 and
its derived processors. */
SET_FLAGS_OSZAPC_LOGIC_8(AL);
set_CF(tmpCF);
set_AF(tmpAF);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::DAS(bxInstruction_c *i)
{
/* The algorithm for DAS is fashioned after the pseudo code in the
* Pentium Processor Family Developer's Manual, volume 3. It seems
* to have changed from earlier processor's manuals. I'm not sure
* if this is a correction in the algorithm printed, or Intel has
* changed the handling of instruction. Validated against Intel
* Pentium family hardware.
*/
Bit8u tmpAL = AL;
int tmpCF = 0, tmpAF = 0;
/* DAS effect the following flags: A,C,S,Z,P */
if (((tmpAL & 0x0F) > 0x09) || get_AF())
{
tmpCF = (AL < 0x06) || get_CF();
AL = AL - 0x06;
tmpAF = 1;
}
if ((tmpAL > 0x99) || get_CF())
{
AL = AL - 0x60;
tmpCF = 1;
}
SET_FLAGS_OSZAPC_LOGIC_8(AL);
set_CF(tmpCF);
set_AF(tmpAF);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::DAA(bxInstruction_c *i)
{
Bit8u tmpAL = AL;
int tmpCF = 0, tmpAF = 0;
/* Validated against Intel Pentium family hardware. */
// DAA affects the following flags: S,Z,A,P,C
if (((tmpAL & 0x0F) > 0x09) || get_AF())
{
tmpCF = ((AL > 0xF9) || get_CF());
AL = AL + 0x06;
tmpAF = 1;
}
if ((tmpAL > 0x99) || get_CF())
{
AL = AL + 0x60;
tmpCF = 1;
}
SET_FLAGS_OSZAPC_LOGIC_8(AL);
set_CF(tmpCF);
set_AF(tmpAF);
BX_NEXT_INSTR(i);
}
Bitu FillFlags(void) {
// if (lflags.type==t_UNKNOWN) return reg_flags;
Bitu new_word=(reg_flags & ~FLAG_MASK);
if (get_CF()) new_word|=FLAG_CF;
if (get_PF()) new_word|=FLAG_PF;
if (get_AF()) new_word|=FLAG_AF;
if (get_ZF()) new_word|=FLAG_ZF;
if (get_SF()) new_word|=FLAG_SF;
if (get_OF()) new_word|=FLAG_OF;
reg_flags=new_word;
lflags.type=t_UNKNOWN;
return reg_flags;
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AAA(bxInstruction_c *i)
{
int tmpCF = 0, tmpAF = 0;
/*
* Note: This instruction incorrectly documented in Intel's materials.
* The right description is:
*
* IF (((AL and 0FH) > 9) or (AF==1)
* THEN
* IF CPU<286 THEN { AL <- AL+6 }
* ELSE { AX <- AX+6 }
* AH <- AH+1
* CF <- 1
* AF <- 1
* ELSE
* CF <- 0
* AF <- 0
* ENDIF
* AL <- AL and 0Fh
*/
/* Validated against Intel Pentium family hardware. */
/* AAA affects the following flags: A,C */
if (((AL & 0x0f) > 9) || get_AF())
{
AX = AX + 0x106;
tmpAF = tmpCF = 1;
}
AL = AL & 0x0f;
/* AAA affects also the following flags: Z,S,O,P */
/* modification of the flags is undocumented */
/* The following behaviour seems to match the P6 and
its derived processors. */
SET_FLAGS_OSZAPC_LOGIC_8(AL);
set_CF(tmpCF);
set_AF(tmpAF);
BX_NEXT_INSTR(i);
}