static void
mcf5282_fec_initialize_hardware(struct mcf5282_enet_struct *sc)
{
int i;
const unsigned char *hwaddr;
rtems_status_code status;
rtems_isr_entry old_handler;
uint32_t clock_speed = get_CPU_clock_speed();
/*
* Issue reset to FEC
*/
MCF5282_FEC_ECR = MCF5282_FEC_ECR_RESET;
rtems_task_wake_after(1);
MCF5282_FEC_ECR = 0;
/*
* Configuration of I/O ports is done outside of this function
*/
#if 0
imm->gpio.pbcnt |= MCF5282_GPIO_PBCNT_SET_FEC; /* Set up port b FEC pins */
#endif
/*
* Set our physical address
*/
hwaddr = sc->arpcom.ac_enaddr;
MCF5282_FEC_PALR = (hwaddr[0] << 24) | (hwaddr[1] << 16) |
(hwaddr[2] << 8) | (hwaddr[3] << 0);
MCF5282_FEC_PAUR = (hwaddr[4] << 24) | (hwaddr[5] << 16);
/*
* Clear the hash table
*/
MCF5282_FEC_GAUR = 0;
MCF5282_FEC_GALR = 0;
/*
* Set up receive buffer size
*/
MCF5282_FEC_EMRBR = 1520; /* Standard Ethernet */
/*
* Allocate mbuf pointers
*/
sc->rxMbuf = malloc(sc->rxBdCount * sizeof *sc->rxMbuf, M_MBUF, M_NOWAIT);
sc->txMbuf = malloc(sc->txBdCount * sizeof *sc->txMbuf, M_MBUF, M_NOWAIT);
if (!sc->rxMbuf || !sc->txMbuf)
rtems_panic("No memory for mbuf pointers");
/*
* Set receiver and transmitter buffer descriptor bases
*/
sc->rxBdBase = mcf5282_bd_allocate(sc->rxBdCount);
sc->txBdBase = mcf5282_bd_allocate(sc->txBdCount);
MCF5282_FEC_ERDSR = (int)sc->rxBdBase;
MCF5282_FEC_ETDSR = (int)sc->txBdBase;
/*
* Set up Receive Control Register:
* Not promiscuous
* MII mode
* Full duplex
* No loopback
*/
MCF5282_FEC_RCR = MCF5282_FEC_RCR_MAX_FL(MAX_MTU_SIZE) |
MCF5282_FEC_RCR_MII_MODE;
/*
* Set up Transmit Control Register:
* Full duplex
* No heartbeat
*/
MCF5282_FEC_TCR = MCF5282_FEC_TCR_FDEN;
/*
* Initialize statistic counters
*/
MCF5282_FEC_MIBC = MCF5282_FEC_MIBC_MIB_DISABLE;
{
vuint32 *vuip = &MCF5282_FEC_RMON_T_DROP;
while (vuip <= &MCF5282_FEC_IEEE_R_OCTETS_OK)
*vuip++ = 0;
}
MCF5282_FEC_MIBC = 0;
/*
* Set MII speed to <= 2.5 MHz
*/
i = (clock_speed + 5000000 - 1) / 5000000;
MCF5282_FEC_MSCR = MCF5282_FEC_MSCR_MII_SPEED(i);
/*
* Set PHYS to 100 Mb/s, full duplex
*/
setMII(1, 0, 0x2100);
setMII(1, 4, 0x0181);
setMII(1, 0, 0x0000);
rtems_task_wake_after(2);
sc->mii_sr2 = getMII(1, 17);
setMII(1, 18, 0x0072);
setMII(1, 0, 0x1000);
/*
* Set up receive buffer descriptors
*/
for (i = 0 ; i < sc->rxBdCount ; i++)
(sc->rxBdBase + i)->status = 0;
/*
* Set up transmit buffer descriptors
*/
for (i = 0 ; i < sc->txBdCount ; i++) {
sc->txBdBase[i].status = 0;
sc->txMbuf[i] = NULL;
}
sc->txBdHead = sc->txBdTail = 0;
sc->txBdActiveCount = 0;
/*
* Set up interrupts
*/
status = rtems_interrupt_catch( mcf5282_fec_tx_interrupt_handler, FEC_INTC0_TX_VECTOR, &old_handler );
if (status != RTEMS_SUCCESSFUL)
rtems_panic ("Can't attach MCF5282 FEC TX interrupt handler: %s\n",
rtems_status_text(status));
status = rtems_interrupt_catch(mcf5282_fec_rx_interrupt_handler, FEC_INTC0_RX_VECTOR, &old_handler);
if (status != RTEMS_SUCCESSFUL)
rtems_panic ("Can't attach MCF5282 FEC RX interrupt handler: %s\n",
rtems_status_text(status));
MCF5282_INTC0_ICR23 = MCF5282_INTC_ICR_IL(FEC_IRQ_LEVEL) |
MCF5282_INTC_ICR_IP(FEC_IRQ_TX_PRIORITY);
MCF5282_INTC0_IMRL &= ~(MCF5282_INTC_IMRL_INT23 | MCF5282_INTC_IMRL_MASKALL);
MCF5282_INTC0_ICR27 = MCF5282_INTC_ICR_IL(FEC_IRQ_LEVEL) |
MCF5282_INTC_ICR_IP(FEC_IRQ_RX_PRIORITY);
MCF5282_INTC0_IMRL &= ~(MCF5282_INTC_IMRL_INT27 | MCF5282_INTC_IMRL_MASKALL);
status = rtems_interrupt_catch(mcf5282_mii_interrupt_handler, MII_VECTOR, &old_handler);
if (status != RTEMS_SUCCESSFUL)
rtems_panic ("Can't attach MCF5282 FEC MII interrupt handler: %s\n",
rtems_status_text(status));
MCF5282_EPORT_EPPAR &= ~MII_EPPAR;
MCF5282_EPORT_EPDDR &= ~MII_EPDDR;
MCF5282_EPORT_EPIER |= MII_EPIER;
MCF5282_INTC0_IMRL &= ~(MCF5282_INTC_IMRL_INT7 | MCF5282_INTC_IMRL_MASKALL);
}
/***************************************************************************
Function : IntUartSet
Description : This updates the hardware UART settings.
***************************************************************************/
static void
IntUartSet(int minor, int baud, int databits, int parity, int stopbits, int hwflow)
{
int divisor;
uint32_t clock_speed;
uint8_t umr1 = 0;
uint8_t umr2 = 0;
struct IntUartInfoStruct *info = &IntUartInfo[minor];
int level;
rtems_interrupt_disable(level);
/* disable interrupts, clear RTS line, and disable the UARTS */
MCF5282_UART_UIMR(minor) = 0;
MCF5282_UART_UOP0(minor) = 1;
MCF5282_UART_UCR(minor) = (MCF5282_UART_UCR_TX_DISABLED | MCF5282_UART_UCR_RX_DISABLED);
/* save the current values */
info->uimr = 0;
info->baud = baud;
info->databits = databits;
info->parity = parity;
info->stopbits = stopbits;
info->hwflow = hwflow;
clock_speed = get_CPU_clock_speed();
/* determine the baud divisor value */
divisor = (clock_speed / ( 32 * baud ));
if ( divisor < 2 )
divisor = 2;
/* check to see if doing hardware flow control */
if ( hwflow )
{
/* set hardware flow options */
umr1 |= MCF5282_UART_UMR1_RXRTS;
umr2 |= MCF5282_UART_UMR2_TXCTS;
}
/* determine the new umr values */
umr1 |= (parity | databits);
umr2 |= (stopbits);
/* reset the uart */
MCF5282_UART_UCR(minor) = MCF5282_UART_UCR_RESET_ERROR;
MCF5282_UART_UCR(minor) = MCF5282_UART_UCR_RESET_RX;
MCF5282_UART_UCR(minor) = MCF5282_UART_UCR_RESET_TX;
/* reset the uart mode register and update values */
MCF5282_UART_UCR(minor) = MCF5282_UART_UCR_RESET_MR;
MCF5282_UART_UMR(minor) = umr1;
MCF5282_UART_UMR(minor) = umr2;
/* set the baud rate values */
MCF5282_UART_UCSR(minor) = (MCF5282_UART_UCSR_RCS_SYS_CLK | MCF5282_UART_UCSR_TCS_SYS_CLK);
MCF5282_UART_UBG1(minor) = (divisor & 0xff00) >> 8;
MCF5282_UART_UBG2(minor) = (divisor & 0x00ff);
/* enable the uart */
MCF5282_UART_UCR(minor) = (MCF5282_UART_UCR_TX_ENABLED | MCF5282_UART_UCR_RX_ENABLED);
/* check to see if interrupts need to be enabled */
if ( info->iomode != TERMIOS_POLLED )
{
/* enable rx interrupts */
info->uimr |= MCF5282_UART_UIMR_FFULL;
MCF5282_UART_UIMR(minor) = info->uimr;
}
/* check to see if doing hardware flow control */
if ( hwflow )
{
/* assert the RTS line */
MCF5282_UART_UOP1(minor) = 1;
}
rtems_interrupt_enable(level);
}
