void set_dma_count(unsigned int chan, unsigned int count) { struct dma_info *info = get_dma_info(chan); struct dma_channel *channel = &info->channels[chan]; channel->count = count; }
void set_dma_mode(unsigned int chan, char mode) { struct dma_info *info = get_dma_info(chan); struct dma_channel *channel = &info->channels[chan]; channel->mode = mode; }
void enable_dma(unsigned int chan) { struct dma_info *info = get_dma_info(chan); struct dma_channel *channel = &info->channels[chan]; info->ops->xfer(channel); }
static int init_fdma_nand(struct stm_nand_emi *data) { const char *dmac_id[] = {STM_DMAC_ID, NULL}; const char *cap_channel[] = {STM_DMA_CAP_LOW_BW, STM_DMA_CAP_HIGH_BW, NULL}; int i; /* Request DMA channel for NAND transactions */ data->dma_chan = request_dma_bycap(dmac_id, cap_channel, NAME); if (data->dma_chan < 0) { printk(KERN_ERR NAME ": request_dma_bycap failed!\n"); return -EBUSY; } /* Initialise DMA paramters */ for (i = 0; i < 2; i++) { dma_params_init(&data->dma_params[i], MODE_FREERUNNING, STM_DMA_LIST_OPEN); dma_params_DIM_1_x_1(&data->dma_params[i]); dma_params_err_cb(&data->dma_params[i], fdma_err, 0, STM_DMA_CB_CONTEXT_TASKLET); } printk(KERN_INFO NAME ": %s assigned %s(%d)\n", data->mtd.name, get_dma_info(data->dma_chan)->name, data->dma_chan); return 0; }
static ssize_t dma_show_devices(struct device *dev, struct device_attribute *attr, char *buf) { ssize_t len = 0; int i; for (i = 0; get_dma_info(i) != NULL; i++) { struct dma_info *info = get_dma_info(i); struct dma_channel *channel = get_dma_channel(i); if (unlikely(!info) || !channel) continue; len += sprintf(buf + len, "%2d: %14s %s\n", channel->chan, info->name, channel->dev_id); } return len; }
void set_dma_addr(unsigned int chan, unsigned int addr) { struct dma_info *info = get_dma_info(chan); struct dma_channel *channel = &info->channels[chan]; /* * Single address mode is the only thing supported through * this interface. */ if ((channel->mode & DMA_MODE_MASK) == DMA_MODE_READ) { channel->sar = addr; } else { channel->dar = addr; } }
static ssize_t dma_show_devices(struct sys_device *dev, char *buf) { ssize_t len = 0; int i; for (i = 0; i < MAX_DMA_CHANNELS; i++) { struct dma_info *info = get_dma_info(i); struct dma_channel *channel = &info->channels[i]; len += sprintf(buf + len, "%2d: %14s %s\n", channel->chan, info->name, channel->dev_id); } return len; }
void daemon_init() { get_dma_info(&membase, &memsize); sbase = membase + config.sbase_offset; initscr(); keypad(stdscr, TRUE); cbreak(); noecho(); timeout(-1); start_color(); init_pair(7, COLOR_BLACK, COLOR_BLACK); init_pair(6, COLOR_RED, COLOR_BLACK); init_pair(5, COLOR_GREEN, COLOR_BLACK); init_pair(4, COLOR_YELLOW, COLOR_BLACK); init_pair(3, COLOR_BLUE, COLOR_BLACK); init_pair(2, COLOR_MAGENTA, COLOR_BLACK); init_pair(1, COLOR_CYAN, COLOR_BLACK); init_pair(0, COLOR_WHITE, COLOR_BLACK); return; }
int mmu_init() { get_dma_info(&membase, &memsize); reg_cpr_write(FKREG_CPR_MMUD, 0, 1); return MEMU_SUCCESS; }