コード例 #1
0
ファイル: sim.cpp プロジェクト: rvbelapure/comparch
void EX_stage() 
{
	if((EX_latch->op_valid) || (!ID_latch->op_valid))
	{
		/* Either MEM has not completed its work ==> pipeline stall
		   Or ID has not yet given any new op ==> No work to do */
		return;
	}
	Op *op = ID_latch->op;
	EX_cycles_completed++;

	if((op->opcode > 0) && (op->opcode < NUM_OP_TYPE))
	{
		// This is a valid opcode
		int oplatency = get_op_latency(op);
		if(EX_cycles_completed != oplatency)
		{
			// Operation not completed. Still more work to do.
			return;
		}
	}

	EX_latch->op = op;
	EX_latch->op_valid = true;
	ID_latch->op_valid = false;
	EX_cycles_completed = 0;
	return;
}
コード例 #2
0
void EX_stage() 
{
  /* you must complete the function */
	static int ex_latency = 0;
	if(ID_latch->op_valid==true)
	{

		if(EX_latch->stage_stall==false) 
		{

			if(ex_latency==0)
				ex_latency=get_op_latency(ID_latch->op);	//check execution latency of op
			ex_latency--;
			if(ex_latency==0)
			{
				ID_latch->op_valid=false;		//set op as invalid for previous stage since op is already transferred
				ID_latch->stage_stall=false;	//if stage stalled remove stall
				EX_latch->op=ID_latch->op;		//transfer pointer to next stage
				EX_latch->op_valid=true;		// set op as valid for the stage

			}
			else
				ID_latch->stage_stall=true;
		}
		else
			ID_latch->stage_stall=true;
	}
}
コード例 #3
0
void EX_stage()
{
   /* The very first execution(for any instrn) in EX_stage would always match the 2nd condition.
      If latency>1 for an instrn, then 1st condition is matched in subsequent cycles in EX stage(so decrement latency)
      Instrn moves to EX latch when latency becomes 0 */
   
  // If any memory stage stall=TRUE, make sure EX_latch valid bit is TRUE so that MEM_stage executes in next cycle. 
  
	

   if(ex_stall==TRUE)
     {
      Op *ex_op=ID_latch->op; // read from ID_latch
      latency--;
      if(latency==0)
       {
    	  ex_stall=FALSE;
    	  EX_latch->op=ex_op; 
    	  EX_latch->op_valid=TRUE;
    	  ID_latch->op_valid=FALSE;
       }
       return;
     }
    
   if(mem_latency_stall==FALSE && mshr_stall==FALSE && ex_stall==FALSE)
        {
        
          if(ID_latch->op_valid==TRUE) 
          {
           Op *ex_op=ID_latch->op; // read from ID_latch
           latency=get_op_latency(ex_op);
      
           if(latency>1)
           	{
        	   ex_stall=TRUE;
        	   latency--;
        	   return;
           	}
           else // single cycle instruction, so pass it to EX latch
           {
        	   EX_latch->op=ex_op; 
        	   EX_latch->op_valid=TRUE;
        	   ID_latch->op_valid=FALSE;
        	   return;
           }
          }
        }
}