void ClockOn(const rtems_irq_connect_data* unused) { uint32_t iocr, r; ppc_cpu_id_t cpu; Clock_driver_ticks = 0; cpu = get_ppc_cpu_type(); if (cpu==PPC_405GP) { iocr = mfdcr(CPC0_CR1); if (bsp_timer_internal_clock) iocr &= ~CR1_CETE ;/* timer clocked from system clock */ else iocr |= CR1_CETE; /* select external timer clock */ mtdcr(CPC0_CR1,iocr); } else if (cpu==PPC_405EX) { mfsdr(SDR0_C405,iocr); if (bsp_timer_internal_clock) iocr &= ~SDR_CETE ;/* timer clocked from system clock */ else iocr |= SDR_CETE; /* select external timer clock */ mtsdr(SDR0_C405,iocr); } else { printk("clock.c:unrecognised CPU"); rtems_fatal_error_occurred(1); } pit_value = rtems_configuration_get_microseconds_per_tick() * bsp_clicks_per_usec; mtspr(PIT,pit_value); tick_time = mfspr(TBL) + pit_value; r = mfspr(TCR); mtspr(TCR, r | PIE | ARE); }
void bsp_start(void) { rtems_status_code sc = RTEMS_SUCCESSFUL; ppc_cpu_id_t myCpu; ppc_cpu_revision_t myCpuRevision; #if defined(MPC55XX_BOARD_MPC5674FEVB) unsigned system_clock_divider = 2; #else unsigned system_clock_divider = 1; #endif null_pointer_protection(); /* * make sure BSS/SBSS is cleared */ memset(&bsp_section_bss_begin [0], 0, (size_t) bsp_section_bss_size); /* * Get CPU identification dynamically. Note that the get_ppc_cpu_type() * function store the result in global variables so that it can be used * latter... */ myCpu = get_ppc_cpu_type(); myCpuRevision = get_ppc_cpu_revision(); /* * determine clock speed */ bsp_clock_speed = mpc55xx_get_system_clock() / system_clock_divider; /* Time reference value */ bsp_clicks_per_usec = bsp_clock_speed / 1000000; /* Initialize exceptions */ ppc_exc_vector_base = (uint32_t) mpc55xx_exc_vector_base; sc = ppc_exc_initialize( PPC_INTERRUPT_DISABLE_MASK_DEFAULT, (uintptr_t) bsp_section_work_begin, Configuration.interrupt_stack_size ); if (sc != RTEMS_SUCCESSFUL) { BSP_panic( "Cannot initialize exceptions"); } ppc_exc_set_handler(ASM_ALIGN_VECTOR, ppc_exc_alignment_handler); /* Initialize interrupts */ sc = bsp_interrupt_initialize(); if (sc != RTEMS_SUCCESSFUL) { BSP_panic( "Cannot initialize interrupts"); } mpc55xx_edma_init(); #ifdef MPC55XX_EMIOS_PRESCALER mpc55xx_emios_initialize(MPC55XX_EMIOS_PRESCALER); #endif }
void bsp_start(void) { unsigned long i = 0; ppc_cpu_id_t myCpu; ppc_cpu_revision_t myCpuRevision; /* * Get CPU identification dynamically. Note that the get_ppc_cpu_type() function * store the result in global variables so that it can be used latter... */ myCpu = get_ppc_cpu_type(); myCpuRevision = get_ppc_cpu_revision(); /* Initialize some device driver parameters */ #ifdef HAS_UBOOT BSP_bus_frequency = bsp_uboot_board_info.bi_busfreq; bsp_clicks_per_usec = bsp_uboot_board_info.bi_busfreq / 8000000; #endif /* HAS_UBOOT */ rtems_counter_initialize_converter(BSP_bus_frequency / 8); /* Initialize some console parameters */ for (i = 0; i < Console_Configuration_Count; ++i) { console_tbl *ct = &Console_Configuration_Ports[i]; ct->ulClock = BSP_bus_frequency; #ifdef HAS_UBOOT if (ct->deviceType == SERIAL_NS16550) { ct->pDeviceParams = (void *) bsp_uboot_board_info.bi_baudrate; } #endif } /* Disable decrementer */ PPC_CLEAR_SPECIAL_PURPOSE_REGISTER_BITS(BOOKE_TCR, BOOKE_TCR_DIE); /* Initialize exception handler */ ppc_exc_initialize_with_vector_base( (uintptr_t) bsp_section_work_begin, rtems_configuration_get_interrupt_stack_size(), bsp_exc_vector_base ); /* Now it is possible to make the code execute only */ qoriq_mmu_change_perm( FSL_EIS_MAS3_SR | FSL_EIS_MAS3_SX, FSL_EIS_MAS3_SX, FSL_EIS_MAS3_SR ); /* Initalize interrupt support */ bsp_interrupt_initialize(); /* Disable boot page translation */ qoriq.lcc.bptr &= ~BPTR_EN; }
/* * BSP start routine. Called by boot_card(). * * This routine does the bulk of the system initialization. */ void bsp_start(void) { uintptr_t intrStackStart; uintptr_t intrStackSize; ppc_cpu_id_t myCpu; ppc_cpu_revision_t myCpuRevision; /* Set the character output function; The application may override this */ BSP_output_char = __bsp_outchar_to_memory; printk("\nWelcome to RTEMS %s\n", _RTEMS_version ); /* * Get CPU identification dynamically. Note that the get_ppc_cpu_type() * function stores the result in global variables so that it can be used later... */ myCpu = get_ppc_cpu_type(); myCpuRevision = get_ppc_cpu_revision(); printk("CPU: 0x%04x, Revision: 0x%04x = %d, Name: %s\n", myCpu, myCpuRevision, myCpuRevision, get_ppc_cpu_type_name(myCpu)); /* * Initialize the device driver parameters */ /* Timebase register ticks/microsecond; The application may override these */ bsp_clicks_per_usec = 350; bsp_timer_internal_clock = true; bsp_timer_average_overhead = 2; bsp_timer_least_valid = 3; /* * Initialize the interrupt related settings. */ intrStackStart = CPU_UP_ALIGN((uint32_t)__bsp_ram_start); intrStackSize = rtems_configuration_get_interrupt_stack_size(); printk(" Base/Start End Size\n" "RAM: 0x%08x 0x%x\n" "RTEMS: 0x%08x\n" "Interrupt Stack: 0x%08x 0x%x\n" "Stack: 0x%08x 0x%08x 0x%x\n" "Workspace: 0x%08x 0x%08x\n" "MsgArea: 0x%08x 0x%x\n" "Physical RAM 0x%08x\n", (uint32_t)RamBase, (uint32_t)RamSize, (uint32_t)__rtems_end, intrStackStart, intrStackSize, (uint32_t)__stack_base, (uint32_t)_stack, (uint32_t)StackSize, (uint32_t)WorkAreaBase, (uint32_t)__bsp_ram_end, (uint32_t)MsgAreaBase, (uint32_t)MsgAreaSize, (uint32_t)__phy_ram_end); /* Continue with application-specific initialization */ app_bsp_start(); }
motorolaBoard getMotorolaBoard(void) { /* * At least the MVME2100 does not have the CPU Type and Base Type Registers, * so it cannot be probed. * * NOTE: Every path must set currentBoard. */ #if defined(mvme2100) currentBoard = (motorolaBoard) MVME_2100; #else unsigned char cpu_type; unsigned char base_mod; ppc_cpu_id_t proc_type; int entry; int mot_entry = -1; cpu_type = inb(MOTOROLA_CPUTYPE_REG) & 0xF0; base_mod = inb(MOTOROLA_BASETYPE_REG); proc_type = get_ppc_cpu_type (); for (entry = 0; mot_boards[entry].cpu_type != 0; entry++) { if ((mot_boards[entry].cpu_type & 0xff) != cpu_type) continue; if ((mot_boards[entry].proc_type != PPC_UNKNOWN) && (mot_boards[entry].proc_type != proc_type)) /* * IMD: processor type does not match * (here we distinguish a MVME2300 and a MVME2400) */ continue; if (mot_boards[entry].base_type != base_mod) continue; else { mot_entry = entry; break; } } if (mot_entry == -1) { printk("Unknown motorola board Please update libbsp/powerpc/shared/motorola/motorola.c\n"); printk("cpu_type = %x\n", (unsigned) cpu_type); printk("base_mod = %x\n", (unsigned) base_mod); currentBoard = MOTOROLA_UNKNOWN; return currentBoard; } currentBoard = (motorolaBoard) mot_entry; #endif return currentBoard; }
/* * bsp_start * * This routine does the bulk of the system initialization. */ void bsp_start( void ) { /* * Note we can not get CPU identification dynamically. * PVR has to be set to PPC_PSIM (0xfffe) from the device * file. */ get_ppc_cpu_type(); /* * initialize the device driver parameters */ BSP_bus_frequency = (unsigned int)&PSIM_INSTRUCTIONS_PER_MICROSECOND; bsp_clicks_per_usec = BSP_bus_frequency; BSP_time_base_divisor = 1; /* * The simulator likes the exception table to be at 0xfff00000. */ bsp_exceptions_in_RAM = FALSE; /* * Initialize default raw exception handlers. */ ppc_exc_initialize( PPC_INTERRUPT_DISABLE_MASK_DEFAULT, (uintptr_t) bsp_section_work_begin, rtems_configuration_get_interrupt_stack_size() ); /* * Initalize RTEMS IRQ system */ BSP_rtems_irq_mng_init(0); /* * Setup BATs and enable MMU */ /* Memory */ setdbat(0, 0x0<<24, 0x0<<24, 2<<24, _PAGE_RW); setibat(0, 0x0<<24, 0x0<<24, 2<<24, 0); /* PCI */ setdbat(1, 0x8<<24, 0x8<<24, 1<<24, IO_PAGE); setdbat(2, 0xc<<24, 0xc<<24, 1<<24, IO_PAGE); _write_MSR(_read_MSR() | MSR_DR | MSR_IR); __asm__ volatile("sync; isync"); }
/* * bsp_start * * This routine does the bulk of the system initialization. */ void bsp_start( void ) { rtems_status_code sc = RTEMS_SUCCESSFUL; ppc_cpu_id_t myCpu; ppc_cpu_revision_t myCpuRevision; /* Get the UART clock initialized first in case we call printk */ InitUARTClock(); Init_FPGA(); EarlyUARTInit(115200); /* * Get CPU identification dynamically. Note that the get_ppc_cpu_type() * function store the result in global variables * so that it can be used later... */ myCpu = get_ppc_cpu_type(); myCpuRevision = get_ppc_cpu_revision(); /* * initialize the device driver parameters */ /* Set globals visible to clock.c */ /* timebase register ticks/microsecond = CPU Clk in MHz */ bsp_clicks_per_usec = 400; bsp_timer_internal_clock = TRUE; bsp_timer_average_overhead = 2; bsp_timer_least_valid = 3; /* * Initialize default raw exception handlers. */ sc = ppc_exc_initialize( PPC_INTERRUPT_DISABLE_MASK_DEFAULT, (uintptr_t) intrStack_start, (uintptr_t) intrStack_size ); if (sc != RTEMS_SUCCESSFUL) { BSP_panic("cannot initialize exceptions"); } /* * Install our own set of exception vectors */ BSP_rtems_irq_mng_init(0); }
void bsp_start(void) { null_pointer_protection(); /* * make sure BSS/SBSS is cleared */ memset(&bsp_section_bss_begin [0], 0, (size_t) bsp_section_bss_size); /* * Get CPU identification dynamically. Note that the get_ppc_cpu_type() * function store the result in global variables so that it can be used * latter... */ get_ppc_cpu_type(); get_ppc_cpu_revision(); /* * determine clock speed */ bsp_clock_speed = mpc55xx_get_system_clock() / MPC55XX_SYSTEM_CLOCK_DIVIDER; /* Time reference value */ bsp_clicks_per_usec = bsp_clock_speed / 1000000; /* Initialize exceptions */ ppc_exc_initialize_with_vector_base( PPC_INTERRUPT_DISABLE_MASK_DEFAULT, (uintptr_t) bsp_section_work_begin, rtems_configuration_get_interrupt_stack_size(), mpc55xx_exc_vector_base ); #ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER ppc_exc_set_handler(ASM_ALIGN_VECTOR, ppc_exc_alignment_handler); #endif /* Initialize interrupts */ bsp_interrupt_initialize(); #if MPC55XX_CHIP_FAMILY != 566 mpc55xx_edma_init(); #endif #ifdef MPC55XX_EMIOS_PRESCALER mpc55xx_emios_initialize(MPC55XX_EMIOS_PRESCALER); #endif }
/* * bsp_start * * This routine does the bulk of the system initialization. */ void bsp_start( void ) { rtems_status_code sc = RTEMS_SUCCESSFUL; ppc_cpu_id_t myCpu; ppc_cpu_revision_t myCpuRevision; /* * Get CPU identification dynamically. Note that the get_ppc_cpu_type() * function store the result in global variables * so that it can be used latter... */ myCpu = get_ppc_cpu_type(); myCpuRevision = get_ppc_cpu_revision(); /* * initialize the device driver parameters */ /* timebase register ticks/microsecond */ bsp_clicks_per_usec = (250000000 / 1000000); bsp_serial_per_sec = 14625000; bsp_serial_external_clock = false; bsp_timer_internal_clock = true; bsp_serial_xon_xoff = false; bsp_serial_cts_rts = false; bsp_serial_rate = 115200; bsp_timer_average_overhead = 2; bsp_timer_least_valid = 3; /* * Initialize default raw exception handlers. */ sc = ppc_exc_initialize( PPC_INTERRUPT_DISABLE_MASK_DEFAULT, (uint32_t)IntrStack_start, IntrStack_end - IntrStack_start ); if (sc != RTEMS_SUCCESSFUL) { BSP_panic("cannot initialize exceptions"); } /* * Install our own set of exception vectors */ BSP_rtems_irq_mng_init(0); }
/* * bsp_start() * * Board-specific initialization code. Called from the generic boot_card() * function defined in rtems/c/src/lib/libbsp/shared/main.c. That function * does some of the board independent initialization. It is called from the * SS555 entry point _start() defined in * rtems/c/src/lib/libbsp/powerpc/ss555/start/start.S * * _start() has set up a stack, has zeroed the .bss section, has set up the * .data section from contents stored in ROM, has turned off interrupts, * and placed the processor in the supervisor mode. boot_card() has left * the processor in that state when bsp_start() was called. * * Input parameters: NONE * * Output parameters: NONE * * Return values: NONE */ void bsp_start(void) { ppc_cpu_id_t myCpu; ppc_cpu_revision_t myCpuRevision; register unsigned char* intrStack; /* * Get CPU identification dynamically. Note that the get_ppc_cpu_type() * function stores the result in global variables so that it can be used * later. */ myCpu = get_ppc_cpu_type(); myCpuRevision = get_ppc_cpu_revision(); /* * Initialize some SPRG registers related to irq handling */ intrStack = (((unsigned char*)&intrStackPtr) - PPC_MINIMUM_STACK_FRAME_SIZE); _write_SPRG1((unsigned int)intrStack); /* * Install our own set of exception vectors */ initialize_exceptions(); /* * initialize the device driver parameters */ bsp_clicks_per_usec = BSP_CRYSTAL_HZ / 4 / 1000000; bsp_clock_speed = BSP_CLOCK_HZ; /* for SCI baud rate generator */ bsp_timer_least_valid = 0; bsp_timer_average_overhead = 0; rtems_counter_initialize_converter(BSP_CRYSTAL_HZ / 4); /* * Initalize RTEMS IRQ system */ BSP_rtems_irq_mng_init(0); }
void bsp_start( void ) { #ifdef CONF_VPD int i; #endif #ifdef SHOW_LCR1_REGISTER unsigned l1cr; #endif #ifdef SHOW_LCR2_REGISTER unsigned l2cr; #endif #ifdef SHOW_LCR3_REGISTER unsigned l3cr; #endif uintptr_t intrStackStart; uintptr_t intrStackSize; ppc_cpu_id_t myCpu; ppc_cpu_revision_t myCpuRevision; Triv121PgTbl pt=0; /* Till Straumann: 4/2005 * Need to map the system registers early, so we can printk... * (otherwise we silently die) */ /* * Kate Feng : PCI 0 domain memory space, want to leave room for the VME window */ setdbat(2, PCI0_MEM_BASE, PCI0_MEM_BASE, 0x10000000, IO_PAGE); /* Till Straumann: 2004 * map the PCI 0, 1 Domain I/O space, GT64260B registers * and the reserved area so that the size is the power of 2. * 2009 : map the entire 256 M space * */ setdbat(3,PCI0_IO_BASE, PCI0_IO_BASE, 0x10000000, IO_PAGE); /* * Get CPU identification dynamically. Note that the get_ppc_cpu_type() function * store the result in global variables so that it can be used latter... */ myCpu = get_ppc_cpu_type(); myCpuRevision = get_ppc_cpu_revision(); #ifdef SHOW_LCR1_REGISTER l1cr = get_L1CR(); printk("Initial L1CR value = %x\n", l1cr); #endif /* * Initialize the interrupt related settings. */ intrStackStart = (uintptr_t) __rtems_end; intrStackSize = rtems_configuration_get_interrupt_stack_size(); /* * Initialize default raw exception handlers. */ ppc_exc_initialize( PPC_INTERRUPT_DISABLE_MASK_DEFAULT, intrStackStart, intrStackSize ); /* * Init MMU block address translation to enable hardware * access * More PCI1 memory mapping to be done after BSP_pgtbl_activate. */ printk("-----------------------------------------\n"); printk("Welcome to %s on MVME5500-0163\n", _RTEMS_version ); printk("-----------------------------------------\n"); BSP_mem_size = probeMemoryEnd(); /* TODO: calculate the BSP_bus_frequency using the REF_CLK bit * of System Status register */ /* rtems_bsp_delay_in_bus_cycles are defined in registers.h */ BSP_bus_frequency = 133333333; BSP_processor_frequency = 1000000000; /* P94 : 7455 clocks the TB/DECR at 1/4 of the system bus clock frequency */ BSP_time_base_divisor = 4000; /* Maybe not setup yet becuase of the warning message */ /* Allocate and set up the page table mappings * This is only available on >604 CPUs. * * NOTE: This setup routine may modify the available memory * size. It is essential to call it before * calculating the workspace etc. */ pt = BSP_pgtbl_setup(&BSP_mem_size); if (!pt) printk("WARNING: unable to setup page tables.\n"); printk("Now BSP_mem_size = 0x%x\n",BSP_mem_size); /* P94 : 7455 TB/DECR is clocked by the system bus clock frequency */ bsp_clicks_per_usec = BSP_bus_frequency/(BSP_time_base_divisor * 1000); /* * Initalize RTEMS IRQ system */ BSP_rtems_irq_mng_init(0); #ifdef SHOW_LCR2_REGISTER l2cr = get_L2CR(); printk("Initial L2CR value = %x\n", l2cr); #endif #ifdef SHOW_LCR3_REGISTER /* L3CR needs DEC int. handler installed for bsp_delay()*/ l3cr = get_L3CR(); printk("Initial L3CR value = %x\n", l3cr); #endif /* Activate the page table mappings only after * initializing interrupts because the irq_mng_init() * routine needs to modify the text */ if (pt) { #ifdef SHOW_MORE_INIT_SETTINGS printk("Page table setup finished; will activate it NOW...\n"); #endif BSP_pgtbl_activate(pt); } /* Read Configuration Vital Product Data (VPD) */ if ( I2Cread_eeprom(0xa8, 4,2, &ConfVPD_buff[0], 150)) printk("I2Cread_eeprom() error \n"); else { #ifdef CONF_VPD printk("\n"); for (i=0; i<150; i++) { printk("%2x ", ConfVPD_buff[i]); if ((i % 20)==0 ) printk("\n"); } printk("\n"); #endif } /* * PCI 1 domain memory space */ setdbat(1, PCI1_MEM_BASE, PCI1_MEM_BASE, 0x10000000, IO_PAGE); #ifdef SHOW_MORE_INIT_SETTINGS printk("Going to start PCI buses scanning and initialization\n"); #endif pci_initialize(); #ifdef SHOW_MORE_INIT_SETTINGS printk("Number of PCI buses found is : %d\n", pci_bus_count()); #endif /* Install our own exception handler (needs PCI) */ globalExceptHdl = BSP_exceptionHandler; /* clear hostbridge errors. MCP signal is not used on the MVME5500 * PCI config space scanning code will trip otherwise :-( */ _BSP_clear_hostbridge_errors(0, 1 /*quiet*/); #ifdef SHOW_MORE_INIT_SETTINGS printk("MSR %x \n", _read_MSR()); printk("Exit from bspstart\n"); #endif }
void bsp_start(void) { extern void *_WorkspaceBase; ppc_cpu_id_t myCpu; ppc_cpu_revision_t myCpuRevision; register unsigned char* intrStack; /* Set MPC8260ADS board LEDS and Uart enable lines */ _BSP_GPLED0_off(); _BSP_GPLED1_off(); _BSP_Uart1_enable(); _BSP_Uart2_enable(); /* * Get CPU identification dynamically. Note that the get_ppc_cpu_type() function * store the result in global variables so that it can be used latter... */ myCpu = get_ppc_cpu_type(); myCpuRevision = get_ppc_cpu_revision(); cpu_init(); /* mmu_init(); */ /* * Initialize some SPRG registers related to irq handling */ intrStack = (((unsigned char*)&intrStackPtr) - PPC_MINIMUM_STACK_FRAME_SIZE); _write_SPRG1((unsigned int)intrStack); /* signal that we have fixed PR288 - eventually, this should go away */ _write_SPRG0(PPC_BSP_HAS_FIXED_PR288); /* printk( "About to call initialize_exceptions\n" ); */ /* * Install our own set of exception vectors */ initialize_exceptions(); /* mmu_init(); */ /* * Enable instruction and data caches. Do not force writethrough mode. */ #if INSTRUCTION_CACHE_ENABLE rtems_cache_enable_instruction(); #endif #if DATA_CACHE_ENABLE rtems_cache_enable_data(); #endif /* * Allocate the memory for the RTEMS Work Space. This can come from * a variety of places: hard coded address, malloc'ed from outside * RTEMS world (e.g. simulator or primitive memory manager), or (as * typically done by stock BSPs) by subtracting the required amount * of work space from the last physical address on the CPU board. */ /* * Need to "allocate" the memory for the RTEMS Workspace and * tell the RTEMS configuration where it is. This memory is * not malloc'ed. It is just "pulled from the air". */ BSP_Configuration.work_space_start = (void *)&_WorkspaceBase; /* BSP_Configuration.microseconds_per_tick = 1000; */ /* * initialize the CPU table for this BSP */ Cpu_table.pretasking_hook = bsp_pretasking_hook; /* init libc, etc. */ Cpu_table.postdriver_hook = bsp_postdriver_hook; if( Cpu_table.interrupt_stack_size < 4*1024 ) Cpu_table.interrupt_stack_size = 4 * 1024; Cpu_table.clicks_per_usec = 10; /* for 40MHz extclk */ Cpu_table.serial_per_sec = 40000000; Cpu_table.serial_external_clock = 0; Cpu_table.serial_xon_xoff = 0; Cpu_table.serial_cts_rts = 0; Cpu_table.serial_rate = 9600; Cpu_table.timer_average_overhead = 3; Cpu_table.timer_least_valid = 3; Cpu_table.clock_speed = 40000000; #ifdef REV_0_2 /* set up some board specific registers */ m8260.siumcr &= 0xF3FFFFFF; /* set TBEN ** BUG FIX ** */ m8260.siumcr |= 0x08000000; #endif /* use BRG1 to generate 32kHz timebase */ /* m8260.brgc1 = M8260_BRG_EN + (uint32_t)(((uint16_t)((40016384)/(32768)) - 1) << 1) + 0; */ /* * Initalize RTEMS IRQ system */ BSP_rtems_irq_mng_init(0); /* * Call this in case we use TERMIOS for console I/O */ m8xx_uart_reserve_resources(&BSP_Configuration); /* rtems_termios_initialize(); */ #ifdef SHOW_MORE_INIT_SETTINGS printk("Exit from bspstart\n"); #endif }
void bsp_start( void) { rtems_status_code sc = RTEMS_SUCCESSFUL; ppc_cpu_id_t myCpu; ppc_cpu_revision_t myCpuRevision; uintptr_t interrupt_stack_start = (uintptr_t) bsp_interrupt_stack_start; uintptr_t interrupt_stack_size = (uintptr_t) bsp_interrupt_stack_size; /* * Get CPU identification dynamically. Note that the get_ppc_cpu_type() function * store the result in global variables so that it can be used latter... */ myCpu = get_ppc_cpu_type(); myCpuRevision = get_ppc_cpu_revision(); /* Basic CPU initialization */ cpu_init(); /* * Enable instruction and data caches. Do not force writethrough mode. */ #if INSTRUCTION_CACHE_ENABLE rtems_cache_enable_instruction(); #endif #if DATA_CACHE_ENABLE rtems_cache_enable_data(); #endif /* * This is evaluated during runtime, so it should be ok to set it * before we initialize the drivers. */ /* Initialize some device driver parameters */ /* * get the (internal) bus frequency * NOTE: the external bus may be clocked at a lower speed * but this does not concern the internal units like PIT, * DEC, baudrate generator etc) */ if (RTEMS_SUCCESSFUL != bsp_tqm_get_cib_uint32("cu", &BSP_bus_frequency)) { BSP_panic("Cannot determine BUS frequency\n"); } bsp_clicks_per_usec = BSP_bus_frequency/1000000/16; bsp_timer_least_valid = 3; bsp_timer_average_overhead = 3; /* Initialize exception handler */ sc = ppc_exc_initialize( PPC_INTERRUPT_DISABLE_MASK_DEFAULT, interrupt_stack_start, interrupt_stack_size ); if (sc != RTEMS_SUCCESSFUL) { BSP_panic("cannot initialize exceptions"); } /* Initalize interrupt support */ sc = bsp_interrupt_initialize(); if (sc != RTEMS_SUCCESSFUL) { BSP_panic("cannot intitialize interrupts"); } #ifdef SHOW_MORE_INIT_SETTINGS printk("Exit from bspstart\n"); #endif }
void bsp_start( void) { rtems_status_code sc = RTEMS_SUCCESSFUL; unsigned long i = 0; ppc_cpu_id_t myCpu; ppc_cpu_revision_t myCpuRevision; uintptr_t interrupt_stack_start = (uintptr_t) bsp_interrupt_stack_start; uintptr_t interrupt_stack_size = (uintptr_t) bsp_interrupt_stack_size; /* * Get CPU identification dynamically. Note that the get_ppc_cpu_type() function * store the result in global variables so that it can be used latter... */ myCpu = get_ppc_cpu_type(); myCpuRevision = get_ppc_cpu_revision(); /* Basic CPU initialization */ cpu_init(); /* * Enable instruction and data caches. Do not force writethrough mode. */ #ifdef BSP_INSTRUCTION_CACHE_ENABLED rtems_cache_enable_instruction(); #endif #ifdef BSP_DATA_CACHE_ENABLED rtems_cache_enable_data(); #endif /* * This is evaluated during runtime, so it should be ok to set it * before we initialize the drivers. */ /* Initialize some device driver parameters */ #ifdef HAS_UBOOT BSP_bus_frequency = bsp_uboot_board_info.bi_busfreq; #else /* HAS_UBOOT */ BSP_bus_frequency = BSP_CLKIN_FRQ * BSP_SYSPLL_MF / BSP_SYSPLL_CKID; #endif /* HAS_UBOOT */ bsp_time_base_frequency = BSP_bus_frequency / 4; bsp_clicks_per_usec = bsp_time_base_frequency / 1000000; /* Initialize some console parameters */ for (i = 0; i < Console_Configuration_Count; ++i) { Console_Configuration_Ports [i].ulClock = BSP_bus_frequency; #ifdef HAS_UBOOT Console_Configuration_Ports [i].pDeviceParams = (void *) bsp_uboot_board_info.bi_baudrate; #endif } /* Initialize exception handler */ #ifndef BSP_DATA_CACHE_ENABLED ppc_exc_cache_wb_check = 0; #endif sc = ppc_exc_initialize( PPC_INTERRUPT_DISABLE_MASK_DEFAULT, interrupt_stack_start, interrupt_stack_size ); if (sc != RTEMS_SUCCESSFUL) { BSP_panic("cannot initialize exceptions"); } /* Install default handler for the decrementer exception */ sc = ppc_exc_set_handler( ASM_DEC_VECTOR, mpc83xx_decrementer_exception_handler); if (sc != RTEMS_SUCCESSFUL) { BSP_panic("cannot install decrementer exception handler"); } /* Initalize interrupt support */ sc = bsp_interrupt_initialize(); if (sc != RTEMS_SUCCESSFUL) { BSP_panic("cannot intitialize interrupts\n"); } #ifdef SHOW_MORE_INIT_SETTINGS printk("Exit from bspstart\n"); #endif }
void bsp_start( void) { rtems_status_code sc = RTEMS_SUCCESSFUL; unsigned long i = 0; /* * Get CPU identification dynamically. Note that the get_ppc_cpu_type() function * store the result in global variables so that it can be used latter... */ get_ppc_cpu_type(); get_ppc_cpu_revision(); /* Basic CPU initialization */ cpu_init(); /* * Enable instruction and data caches. Do not force writethrough mode. */ #ifdef BSP_INSTRUCTION_CACHE_ENABLED rtems_cache_enable_instruction(); #endif #ifdef BSP_DATA_CACHE_ENABLED rtems_cache_enable_data(); #endif /* * This is evaluated during runtime, so it should be ok to set it * before we initialize the drivers. */ /* Initialize some device driver parameters */ #ifdef HAS_UBOOT BSP_bus_frequency = bsp_uboot_board_info.bi_busfreq; #else /* HAS_UBOOT */ BSP_bus_frequency = BSP_CLKIN_FRQ * BSP_SYSPLL_MF / BSP_SYSPLL_CKID; #endif /* HAS_UBOOT */ bsp_time_base_frequency = BSP_bus_frequency / 4; bsp_clicks_per_usec = bsp_time_base_frequency / 1000000; rtems_counter_initialize_converter(bsp_time_base_frequency); /* Initialize some console parameters */ for (i = 0; i < console_device_count; ++i) { ns16550_context *ctx = (ns16550_context *) console_device_table[i].context; ctx->clock = BSP_bus_frequency; #ifdef HAS_UBOOT ctx->initial_baud = bsp_uboot_board_info.bi_baudrate; #endif } /* Initialize exception handler */ #ifndef BSP_DATA_CACHE_ENABLED ppc_exc_cache_wb_check = 0; #endif ppc_exc_initialize( (uintptr_t) bsp_section_work_begin, rtems_configuration_get_interrupt_stack_size() ); /* Install default handler for the decrementer exception */ sc = ppc_exc_set_handler( ASM_DEC_VECTOR, mpc83xx_decrementer_exception_handler); if (sc != RTEMS_SUCCESSFUL) { rtems_panic("cannot install decrementer exception handler"); } /* Initalize interrupt support */ bsp_interrupt_initialize(); #ifdef SHOW_MORE_INIT_SETTINGS printk("Exit from bspstart\n"); #endif }
void bsp_start(void) { unsigned long i = 0; /* * Get CPU identification dynamically. Note that the get_ppc_cpu_type() function * store the result in global variables so that it can be used latter... */ get_ppc_cpu_type(); get_ppc_cpu_revision(); /* Initialize some device driver parameters */ #ifdef HAS_UBOOT BSP_bus_frequency = bsp_uboot_board_info.bi_busfreq / QORIQ_BUS_CLOCK_DIVIDER; bsp_clicks_per_usec = BSP_bus_frequency / 8000000; rtems_counter_initialize_converter( #ifdef __PPC_CPU_E6500__ bsp_uboot_board_info.bi_intfreq #else BSP_bus_frequency / 8 #endif ); #endif /* HAS_UBOOT */ /* Initialize some console parameters */ for (i = 0; i < console_device_count; ++i) { const console_device *dev = &console_device_table[i]; const rtems_termios_device_handler *ns16550 = #ifdef BSP_USE_UART_INTERRUPTS &ns16550_handler_interrupt; #else &ns16550_handler_polled; #endif if (dev->handler == ns16550) { ns16550_context *ctx = (ns16550_context *) dev->context; ctx->clock = BSP_bus_frequency; #ifdef HAS_UBOOT #ifdef U_BOOT_GENERIC_BOARD_INFO ctx->initial_baud = 115200; #else ctx->initial_baud = bsp_uboot_board_info.bi_baudrate; #endif #endif } } /* Initialize exception handler */ ppc_exc_initialize_with_vector_base( (uintptr_t) bsp_section_work_begin, rtems_configuration_get_interrupt_stack_size(), bsp_exc_vector_base ); /* Now it is possible to make the code execute only */ qoriq_mmu_change_perm( FSL_EIS_MAS3_SR | FSL_EIS_MAS3_SX, FSL_EIS_MAS3_SX, FSL_EIS_MAS3_SR ); /* Initalize interrupt support */ bsp_interrupt_initialize(); rtems_cache_coherent_add_area( bsp_section_nocacheheap_begin, (uintptr_t) bsp_section_nocacheheap_size ); /* Disable boot page translation */ #if QORIQ_CHIP_IS_T_VARIANT(QORIQ_CHIP_VARIANT) qoriq.lcc.bstar &= ~LCC_BSTAR_EN; #else qoriq.lcc.bptr &= ~BPTR_EN; #endif }
/* * bsp_start() * * Board-specific initialization code. Called from the generic boot_card() * function defined in rtems/c/src/lib/libbsp/shared/main.c. That function * does some of the board independent initialization. It is called from the * MBX8xx entry point _start() defined in * rtems/c/src/lib/libbsp/powerpc/mbx8xx/startup/start.S * * _start() has set up a stack, has zeroed the .bss section, has turned off * interrupts, and placed the processor in the supervisor mode. boot_card() * has left the processor in that state when bsp_start() was called. * * RUNS WITH ADDRESS TRANSLATION AND CACHING TURNED OFF! * ASSUMES THAT THE VIRTUAL ADDRESSES WILL BE IDENTICAL TO THE PHYSICAL * ADDRESSES. Software-controlled address translation would be required * otherwise. * * Input parameters: NONE * * Output parameters: NONE * * Return values: NONE */ void bsp_start(void) { ppc_cpu_id_t myCpu; ppc_cpu_revision_t myCpuRevision; /* * Get CPU identification dynamically. Note that the get_ppc_cpu_type() function * store the result in global variables so that it can be used latter... */ myCpu = get_ppc_cpu_type(); myCpuRevision = get_ppc_cpu_revision(); mmu_init(); /* * Enable instruction and data caches. Do not force writethrough mode. */ #if NVRAM_CONFIGURE == 1 if ( nvram->cache_mode & 0x02 ) rtems_cache_enable_instruction(); if ( nvram->cache_mode & 0x01 ) rtems_cache_enable_data(); #else #if BSP_INSTRUCTION_CACHE_ENABLED rtems_cache_enable_instruction(); #endif #if BSP_DATA_CACHE_ENABLED rtems_cache_enable_data(); #endif #endif /* Initialize exception handler */ ppc_exc_initialize( PPC_INTERRUPT_DISABLE_MASK_DEFAULT, (uintptr_t) IntrStack_start, (uintptr_t) intrStack - (uintptr_t) IntrStack_start ); /* Initalize interrupt support */ bsp_interrupt_initialize(); /* * initialize the device driver parameters */ #if ( defined(mbx860_001b) || \ defined(mbx860_002b) || \ defined(mbx860_003b) || \ defined(mbx860_003b) || \ defined(mbx860_004b) || \ defined(mbx860_005b) || \ defined(mbx860_006b) || \ defined(mbx821_001b) || \ defined(mbx821_002b) || \ defined(mbx821_003b) || \ defined(mbx821_004b) || \ defined(mbx821_005b) || \ defined(mbx821_006b)) bsp_clicks_per_usec = 0; /* for 32768Hz extclk */ #else bsp_clicks_per_usec = 1; /* for 4MHz extclk */ #endif bsp_serial_per_sec = 10000000; bsp_serial_external_clock = true; bsp_serial_xon_xoff = false; bsp_serial_cts_rts = true; bsp_serial_rate = 9600; #if ( defined(mbx821_001) || defined(mbx821_001b) || defined(mbx860_001b) ) bsp_clock_speed = 50000000; bsp_timer_average_overhead = 3; bsp_timer_least_valid = 3; #else bsp_clock_speed = 40000000; bsp_timer_average_overhead = 3; bsp_timer_least_valid = 3; #endif m8xx.scc2.sccm=0; m8xx.scc2p.rbase=0; m8xx.scc2p.tbase=0; m8xx_cp_execute_cmd( M8xx_CR_OP_STOP_TX | M8xx_CR_CHAN_SCC2 ); #ifdef SHOW_MORE_INIT_SETTINGS printk("Exit from bspstart\n"); #endif }
void bsp_start( void ) { rtems_status_code sc = RTEMS_SUCCESSFUL; #if !defined(mvme2100) unsigned l2cr; #endif uintptr_t intrStackStart; uintptr_t intrStackSize; ppc_cpu_id_t myCpu; ppc_cpu_revision_t myCpuRevision; prep_t boardManufacturer; motorolaBoard myBoard; Triv121PgTbl pt=0; /* * Get CPU identification dynamically. Note that the get_ppc_cpu_type() * function store the result in global variables so that it can be used * later... */ myCpu = get_ppc_cpu_type(); myCpuRevision = get_ppc_cpu_revision(); /* * Init MMU block address translation to enable hardware access */ #if !defined(mvme2100) /* * PC legacy IO space used for inb/outb and all PC compatible hardware */ setdbat(1, _IO_BASE, _IO_BASE, 0x10000000, IO_PAGE); #endif /* * PCI devices memory area. Needed to access OpenPIC features * provided by the Raven * * T. Straumann: give more PCI address space */ setdbat(2, PCI_MEM_BASE+PCI_MEM_WIN0, PCI_MEM_BASE+PCI_MEM_WIN0, 0x10000000, IO_PAGE); /* * Must have acces to open pic PCI ACK registers provided by the RAVEN */ setdbat(3, 0xf0000000, 0xf0000000, 0x10000000, IO_PAGE); #if defined(mvme2100) /* Need 0xfec00000 mapped for this */ EUMBBAR = get_eumbbar(); #endif /* * enables L1 Cache. Note that the L1_caches_enables() codes checks for * relevant CPU type so that the reason why there is no use of myCpu... */ L1_caches_enables(); #if !defined(mvme2100) /* * Enable L2 Cache. Note that the set_L2CR(L2CR) codes checks for * relevant CPU type (mpc750)... */ l2cr = get_L2CR(); #ifdef SHOW_LCR2_REGISTER printk("Initial L2CR value = %x\n", l2cr); #endif if ( (! (l2cr & 0x80000000)) && ((int) l2cr == -1)) set_L2CR(0xb9A14000); #endif /* * Initialize the interrupt related settings. */ intrStackStart = (uintptr_t) __rtems_end; intrStackSize = rtems_configuration_get_interrupt_stack_size(); /* * Initialize default raw exception handlers. */ sc = ppc_exc_initialize( PPC_INTERRUPT_DISABLE_MASK_DEFAULT, intrStackStart, intrStackSize ); if (sc != RTEMS_SUCCESSFUL) { BSP_panic("cannot initialize exceptions"); } select_console(CONSOLE_LOG); /* * We check that the keyboard is present and immediately * select the serial console if not. */ #if defined(BSP_KBD_IOBASE) { int err; err = kbdreset(); if (err) select_console(CONSOLE_SERIAL); } #else select_console(CONSOLE_SERIAL); #endif boardManufacturer = checkPrepBoardType(&residualCopy); if (boardManufacturer != PREP_Motorola) { printk("Unsupported hardware vendor\n"); while (1); } myBoard = getMotorolaBoard(); printk("-----------------------------------------\n"); printk("Welcome to %s on %s\n", _RTEMS_version, motorolaBoardToString(myBoard)); printk("-----------------------------------------\n"); #ifdef SHOW_MORE_INIT_SETTINGS printk("Residuals are located at %x\n", (unsigned) &residualCopy); printk("Additionnal boot options are %s\n", loaderParam); printk("Initial system stack at %x\n",stack); printk("Software IRQ stack starts at %x with size %u\n", intrStackStart, intrStackSize); printk("-----------------------------------------\n"); #endif #ifdef TEST_RETURN_TO_PPCBUG printk("Hit <Enter> to return to PPCBUG monitor\n"); printk("When Finished hit GO. It should print <Back from monitor>\n"); debug_getc(); _return_to_ppcbug(); printk("Back from monitor\n"); _return_to_ppcbug(); #endif /* TEST_RETURN_TO_PPCBUG */ #ifdef SHOW_MORE_INIT_SETTINGS printk("Going to start PCI buses scanning and initialization\n"); #endif pci_initialize(); { const struct _int_map *bspmap = motorolaIntMap(currentBoard); if( bspmap ) { printk("pci : Configuring interrupt routing for '%s'\n", motorolaBoardToString(currentBoard)); FixupPCI(bspmap, motorolaIntSwizzle(currentBoard)); } else printk("pci : Interrupt routing not available for this bsp\n"); } #ifdef SHOW_MORE_INIT_SETTINGS printk("Number of PCI buses found is : %d\n", pci_bus_count()); #endif #ifdef TEST_RAW_EXCEPTION_CODE printk("Testing exception handling Part 1\n"); /* * Cause a software exception */ __asm__ __volatile ("sc"); /* * Check we can still catch exceptions and return coorectly. */ printk("Testing exception handling Part 2\n"); __asm__ __volatile ("sc"); /* * Somehow doing the above seems to clobber SPRG0 on the mvme2100. The * interrupt disable mask is stored in SPRG0. Is this a problem? */ ppc_interrupt_set_disable_mask( PPC_INTERRUPT_DISABLE_MASK_DEFAULT); #endif /* See above */ BSP_mem_size = residualCopy.TotalMemory; BSP_bus_frequency = residualCopy.VitalProductData.ProcessorBusHz; BSP_processor_frequency = residualCopy.VitalProductData.ProcessorHz; BSP_time_base_divisor = (residualCopy.VitalProductData.TimeBaseDivisor? residualCopy.VitalProductData.TimeBaseDivisor : 4000); /* clear hostbridge errors but leave MCP disabled - * PCI config space scanning code will trip otherwise :-( */ _BSP_clear_hostbridge_errors(0 /* enableMCP */, 0/*quiet*/); /* Allocate and set up the page table mappings * This is only available on >604 CPUs. * * NOTE: This setup routine may modify the available memory * size. It is essential to call it before * calculating the workspace etc. */ pt = BSP_pgtbl_setup(&BSP_mem_size); if (!pt || TRIV121_MAP_SUCCESS != triv121PgTblMap( pt, TRIV121_121_VSID, 0xfeff0000, 1, TRIV121_ATTR_IO_PAGE, TRIV121_PP_RW_PAGE)) { printk("WARNING: unable to setup page tables VME " "bridge must share PCI space\n"); } /* * initialize the device driver parameters */ bsp_clicks_per_usec = BSP_bus_frequency/(BSP_time_base_divisor * 1000); /* * Initalize RTEMS IRQ system */ BSP_rtems_irq_mng_init(0); /* Activate the page table mappings only after * initializing interrupts because the irq_mng_init() * routine needs to modify the text */ if (pt) { #ifdef SHOW_MORE_INIT_SETTINGS printk("Page table setup finished; will activate it NOW...\n"); #endif BSP_pgtbl_activate(pt); /* finally, switch off DBAT3 */ setdbat(3, 0, 0, 0, 0); } #if defined(DEBUG_BATS) ShowBATS(); #endif #ifdef SHOW_MORE_INIT_SETTINGS printk("Exit from bspstart\n"); #endif }
/* * bsp_start() * * Board-specific initialization code. Called from the generic boot_card() * function defined in rtems/c/src/lib/libbsp/shared/main.c. That function * does some of the board independent initialization. It is called from the * SS555 entry point _start() defined in * rtems/c/src/lib/libbsp/powerpc/ss555/startup/start.S * * _start() has set up a stack, has zeroed the .bss section, has set up the * .data section from contents stored in ROM, has turned off interrupts, * and placed the processor in the supervisor mode. boot_card() has left * the processor in that state when bsp_start() was called. * * Input parameters: NONE * * Output parameters: NONE * * Return values: NONE */ void bsp_start(void) { extern char _WorkspaceBase[]; ppc_cpu_id_t myCpu; ppc_cpu_revision_t myCpuRevision; register unsigned char* intrStack; /* * Get CPU identification dynamically. Note that the get_ppc_cpu_type() * function stores the result in global variables so that it can be used * later. */ myCpu = get_ppc_cpu_type(); myCpuRevision = get_ppc_cpu_revision(); /* * Initialize some SPRG registers related to irq handling */ intrStack = (((unsigned char*)&intrStackPtr) - PPC_MINIMUM_STACK_FRAME_SIZE); _write_SPRG1((unsigned int)intrStack); /* signal them that we have fixed PR288 - eventually, this should go away */ _write_SPRG0(PPC_BSP_HAS_FIXED_PR288); /* * Install our own set of exception vectors */ initialize_exceptions(); /* * Allocate the memory for the RTEMS Work Space. This can come from * a variety of places: hard coded address, malloc'ed from outside * RTEMS world (e.g. simulator or primitive memory manager), or (as * typically done by stock BSPs) by subtracting the required amount * of work space from the last physical address on the CPU board. * * In this case, the memory is not malloc'ed. It is just * "pulled from the air". */ BSP_Configuration.work_space_start = _WorkspaceBase; /* * initialize the CPU table for this BSP */ Cpu_table.pretasking_hook = bsp_pretasking_hook; /* init libc, etc. */ Cpu_table.postdriver_hook = bsp_postdriver_hook; if( Cpu_table.interrupt_stack_size < 4 * 1024 ) Cpu_table.interrupt_stack_size = 4 * 1024; Cpu_table.clicks_per_usec = BSP_CRYSTAL_HZ / 4 / 1000000; Cpu_table.clock_speed = BSP_CLOCK_HZ; /* for SCI baud rate generator */ /* * Call this in case we use TERMIOS for console I/O */ m5xx_uart_reserve_resources( &BSP_Configuration ); /* * Initalize RTEMS IRQ system */ BSP_rtems_irq_mng_init(0); }
void bsp_start(void) { rtems_status_code sc = RTEMS_SUCCESSFUL; ppc_cpu_id_t myCpu; ppc_cpu_revision_t myCpuRevision; /* Set MPC8260ADS board LEDS and Uart enable lines */ _BSP_GPLED0_off(); _BSP_GPLED1_off(); _BSP_Uart1_enable(); _BSP_Uart2_enable(); /* * Get CPU identification dynamically. Note that the get_ppc_cpu_type() function * store the result in global variables so that it can be used latter... */ myCpu = get_ppc_cpu_type(); myCpuRevision = get_ppc_cpu_revision(); cpu_init(); /* mmu_init(); */ /* Initialize exception handler */ /* FIXME: Interrupt stack begin and size */ sc = ppc_exc_initialize( PPC_INTERRUPT_DISABLE_MASK_DEFAULT, (uintptr_t) IntrStack_start, (uintptr_t) intrStack - (uintptr_t) IntrStack_start ); if (sc != RTEMS_SUCCESSFUL) { BSP_panic("cannot intitialize exceptions"); } /* Initalize interrupt support */ sc = bsp_interrupt_initialize(); if (sc != RTEMS_SUCCESSFUL) { BSP_panic("cannot intitialize interrupts"); } /* mmu_init(); */ /* * Enable instruction and data caches. Do not force writethrough mode. */ #if INSTRUCTION_CACHE_ENABLE rtems_cache_enable_instruction(); #endif #if DATA_CACHE_ENABLE rtems_cache_enable_data(); #endif /* * initialize the device driver parameters */ bsp_clicks_per_usec = 10; /* for 40MHz extclk */ bsp_serial_per_sec = 40000000; bsp_serial_external_clock = 0; bsp_serial_xon_xoff = 0; bsp_serial_cts_rts = 0; bsp_serial_rate = 9600; bsp_timer_average_overhead = 3; bsp_timer_least_valid = 3; bsp_clock_speed = 40000000; #ifdef REV_0_2 /* set up some board specific registers */ m8260.siumcr &= 0xF3FFFFFF; /* set TBEN ** BUG FIX ** */ m8260.siumcr |= 0x08000000; #endif /* use BRG1 to generate 32kHz timebase */ /* m8260.brgc1 = M8260_BRG_EN + (uint32_t)(((uint16_t)((40016384)/(32768)) - 1) << 1) + 0; */ #ifdef SHOW_MORE_INIT_SETTINGS printk("Exit from bspstart\n"); #endif }
void bsp_start(void) { ppc_cpu_id_t myCpu; ppc_cpu_revision_t myCpuRevision; /* * Get CPU identification dynamically. Note that the get_ppc_cpu_type() * function store the result in global variables so that it can be used * later... */ myCpu = get_ppc_cpu_type(); myCpuRevision = get_ppc_cpu_revision(); #if defined(HAS_UBOOT) && defined(SHOW_MORE_INIT_SETTINGS) { void dumpUBootBDInfo( bd_t * ); dumpUBootBDInfo( &bsp_uboot_board_info ); } #endif cpu_init(); if(get_ppc_cpu_revision() >= 0x2014) { /* Special settings for MPC5200B (B variant) */ uint32_t xlb_cfg = mpc5200.config; /* XXX: The Freescale documentation for BSDIS seems to be wrong */ xlb_cfg |= XLB_CFG_BSDIS; xlb_cfg &= ~XLB_CFG_PLDIS; mpc5200.config = xlb_cfg; } bsp_time_base_frequency = XLB_CLOCK / 4; bsp_clicks_per_usec = (XLB_CLOCK/4000000); /* Initialize exception handler */ ppc_exc_cache_wb_check = 0; ppc_exc_initialize( PPC_INTERRUPT_DISABLE_MASK_DEFAULT, (uintptr_t) bsp_interrupt_stack_start, (uintptr_t) bsp_interrupt_stack_size ); ppc_exc_set_handler(ASM_ALIGN_VECTOR, ppc_exc_alignment_handler); /* Initalize interrupt support */ bsp_interrupt_initialize(); /* * If the BSP was built with IRQ benchmarking enabled, * then intialize it. */ #if (BENCHMARK_IRQ_PROCESSING == 1) BSP_IRQ_Benchmarking_Reset(); #endif #ifdef SHOW_MORE_INIT_SETTINGS printk("Exit from bspstart\n"); #endif }
rtems_device_driver Clock_initialize( rtems_device_major_number major, rtems_device_minor_number minor, void *arg) { /* Current CPU type */ ppc_cpu_id_t cpu_type = get_ppc_cpu_type(); /* Make major/minor available to others such as shared memory driver */ rtems_clock_major = major; rtems_clock_minor = minor; /* * Set default ticker. * * The function rtems_clock_tick() returns a status code. This value * will be discarded since the RTEMS documentation claims that it is * always successful. */ ppc_clock_tick = (void (*)(void)) rtems_clock_tick; /* Set the decrementer to the maximum value */ ppc_set_decrementer_register( PPC_CLOCK_DECREMENTER_MAX); /* Decrementer value */ ppc_clock_decrementer_value = bsp_clicks_per_usec * rtems_configuration_get_microseconds_per_tick() - 1; /* Check decrementer value */ if (ppc_clock_decrementer_value == 0) { ppc_clock_decrementer_value = PPC_CLOCK_DECREMENTER_MAX; RTEMS_SYSLOG_ERROR( "decrementer value would be zero, will be set to maximum value instead\n"); } /* Set the nanoseconds since last tick handler */ rtems_clock_set_nanoseconds_extension( ppc_clock_nanoseconds_since_last_tick); if (ppc_cpu_is_bookE()) { /* Set decrementer auto-reload value */ PPC_SET_SPECIAL_PURPOSE_REGISTER( BOOKE_DECAR, ppc_clock_decrementer_value); /* Install exception handler */ ppc_exc_set_handler( ASM_BOOKE_DEC_VECTOR, ppc_clock_exception_handler_booke); /* Enable decrementer and auto-reload */ PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS( BOOKE_TCR, BOOKE_TCR_DIE | BOOKE_TCR_ARE); } else if (cpu_type == PPC_e300c2 || cpu_type == PPC_e300c3) { /* TODO: Not tested for e300c2 */ /* Enable auto-reload */ PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS( HID0, 0x00000040); /* Install exception handler */ ppc_exc_set_handler( ASM_DEC_VECTOR, ppc_clock_exception_handler_e300); } else { /* Here the decrementer value is actually the interval */ ++ppc_clock_decrementer_value; /* Initialize next time base */ ppc_clock_next_time_base = ppc_time_base() + ppc_clock_decrementer_value; /* Install exception handler */ ppc_exc_set_handler( ASM_DEC_VECTOR, ppc_clock_exception_handler_first); } /* Set the decrementer value */ ppc_set_decrementer_register( ppc_clock_decrementer_value); return RTEMS_SUCCESSFUL; }