static void __init periph_clk_init(void __iomem *clk_base, struct tegra_clk *tegra_clks) { int i; struct clk *clk; struct clk **dt_clk; for (i = 0; i < ARRAY_SIZE(periph_clks); i++) { struct tegra_clk_periph_regs *bank; struct tegra_periph_init_data *data; data = periph_clks + i; dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks); if (!dt_clk) continue; bank = get_reg_bank(data->periph.gate.clk_num); if (!bank) continue; data->periph.gate.regs = bank; clk = tegra_clk_register_periph(data->name, data->p.parent_names, data->num_parents, &data->periph, clk_base, data->offset, data->flags); *dt_clk = clk; } }
static void __init periph_clk_init(void __iomem *clk_base, struct tegra_clk *tegra_clks) { int i; struct clk *clk; struct clk **dt_clk; for (i = 0; i < ARRAY_SIZE(periph_clks); i++) { const struct tegra_clk_periph_regs *bank; struct tegra_periph_init_data *data; data = periph_clks + i; dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks); if (!dt_clk) continue; bank = get_reg_bank(data->periph.gate.clk_num); if (!bank) continue; data->periph.gate.regs = bank; clk = tegra_clk_register_periph_data(clk_base, data); *dt_clk = clk; } }
static struct clk *_tegra_clk_register_periph(const char *name, const char **parent_names, int num_parents, struct tegra_clk_periph *periph, void __iomem *clk_base, u32 offset, unsigned long flags) { struct clk *clk; struct clk_init_data init; struct tegra_clk_periph_regs *bank; bool div = !(periph->gate.flags & TEGRA_PERIPH_NO_DIV); if (periph->gate.flags & TEGRA_PERIPH_NO_DIV) { flags |= CLK_SET_RATE_PARENT; init.ops = &tegra_clk_periph_nodiv_ops; } else if (periph->gate.flags & TEGRA_PERIPH_NO_GATE) init.ops = &tegra_clk_periph_no_gate_ops; else init.ops = &tegra_clk_periph_ops; init.name = name; init.flags = flags; init.parent_names = parent_names; init.num_parents = num_parents; bank = get_reg_bank(periph->gate.clk_num); if (!bank) return ERR_PTR(-EINVAL); /* Data in .init is copied by clk_register(), so stack variable OK */ periph->hw.init = &init; periph->magic = TEGRA_CLK_PERIPH_MAGIC; periph->mux.reg = clk_base + offset; periph->divider.reg = div ? (clk_base + offset) : NULL; periph->gate.clk_base = clk_base; periph->gate.regs = bank; periph->gate.enable_refcnt = periph_clk_enb_refcnt; clk = clk_register(NULL, &periph->hw); if (IS_ERR(clk)) return clk; periph->mux.hw.clk = clk; periph->divider.hw.clk = div ? clk : NULL; periph->gate.hw.clk = clk; return clk; }