int32_t __init wdt_init_module(void)
{
printk("Load Kernel WDG Timer Module\n");
/*
* System Clock = CPU Clock/2
* For user easy configuration, We assume the unit of watch dog timer is 1s,
* so we need to calculate the TMR1LOAD value.
*
* Unit= 1/(SysClk/65536), 1 Sec = (SysClk)/65536
*
*/
// initialize WDG timer (Timer1)
setup_wdg_timer(&wdg_timer, refresh_wdg_timer, 0);
set_wdg_timer_mode(TMR1CTL,WATCHDOG);
set_wdg_timer_clock_prescale(TMR1CTL,SYS_CLK_DIV65536);
wdg_load_value = CONFIG_RALINK_WDG_TIMER * (get_surfboard_sysclk()/65536);
#if defined (CONFIG_RALINK_RT2880) || defined (CONFIG_RALINK_RT2883) || \
defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3883)
wdg_load_value = CONFIG_RALINK_WDG_TIMER * (get_surfboard_sysclk()/65536);
#else
wdg_load_value = CONFIG_RALINK_WDG_TIMER * (40000000/65536); //fixed at 40Mhz
#endif
refresh_wdg_timer(wdg_load_value);
set_wdg_timer_ebl(TMR1CTL,1);
return 0;
}
int spic_init(void)
{
// GPIO-SPI mode
ra_and(RALINK_REG_GPIOMODE, ~(1 << 1)); //use normal(SPI) mode instead of GPIO mode
/* reset spi block */
ra_or(RT2880_RSTCTRL_REG, RSTCTRL_SPI_RESET);
udelay(1);
ra_and(RT2880_RSTCTRL_REG, ~RSTCTRL_SPI_RESET);
udelay(1);
#if defined(CONFIG_RALINK_VITESSE_SWITCH_CONNECT_SPI_CS1)||defined(CONFIG_RALINK_SLIC_CONNECT_SPI_CS1)
/* config ARB and set the low or high active correctly according to the device */
ra_outl(RT2880_SPI_ARB_REG, SPIARB_ARB_EN|(SPIARB_SPI1_ACTIVE_MODE<<1)| SPIARB_SPI0_ACTIVE_MODE);
ra_outl(RT2880_SPI1_CTL_REG, (~SPIARB_SPI1_ACTIVE_MODE)&0x1);
#endif
ra_outl(RT2880_SPI0_CTL_REG, (~SPIARB_SPI0_ACTIVE_MODE)&0x1);
// FIXME, clk_div should depend on spi-flash.
// mode 0 (SPICLKPOL = 0) & (RXCLKEDGE_FALLING = 0)
// mode 3 (SPICLKPOL = 1) & (RXCLKEDGE_FALLING = 0)
ra_outl(RT2880_SPICFG_REG, SPICFG_MSBFIRST | SPICFG_TXCLKEDGE_FALLING | CFG_CLK_DIV | SPICFG_SPICLKPOL );
// set idle state
ra_outl(RT2880_SPICTL_REG, SPICTL_HIZSDO | SPICTL_SPIENA_HIGH);
spi_wait_nsec = (8 * 1000 / ((get_surfboard_sysclk() / 1000 / 1000 / CFG_CLK_DIV) )) >> 1 ;
//printk("spi_wait_nsec: %x \n", spi_wait_nsec);
return 0;
}
int spic_init(void)
{
/* use normal SPI mode instead of GPIO mode */
ra_and(RALINK_REG_GPIOMODE, ~(RALINK_GPIOMODE_SPI));
/* reset spi block */
ra_or(RT2880_RSTCTRL_REG, RSTCTRL_SPI_RESET);
udelay(1);
ra_and(RT2880_RSTCTRL_REG, ~RSTCTRL_SPI_RESET);
udelay(1);
#if defined(CONFIG_RALINK_VITESSE_SWITCH_CONNECT_SPI_CS1)||defined(CONFIG_RALINK_SLIC_CONNECT_SPI_CS1)
/* config ARB and set the low or high active correctly according to the device */
ra_outl(RT2880_SPI_ARB_REG, SPIARB_ARB_EN|(SPIARB_SPI1_ACTIVE_MODE<<1)| SPIARB_SPI0_ACTIVE_MODE);
ra_outl(RT2880_SPI1_CTL_REG, (~SPIARB_SPI1_ACTIVE_MODE)&0x1);
#endif
ra_outl(RT2880_SPI0_CTL_REG, (~SPIARB_SPI0_ACTIVE_MODE)&0x1);
#if !defined (COMMAND_MODE)
ra_outl(RT2880_SPICFG_REG, SPICFG_MSBFIRST | SPICFG_RXCLKEDGE_FALLING | SPICFG_TXCLKEDGE_FALLING | CFG_CLK_DIV);
#else
ra_outl(RT2880_SPICFG_REG, SPICFG_MSBFIRST | SPICFG_TXCLKEDGE_FALLING | SPICFG_SPICLKPOL | CFG_CLK_DIV );
#endif
// set idle state
ra_outl(RT2880_SPICTL_REG, SPICTL_HIZSDO | SPICTL_SPIENA_HIGH);
spi_wait_nsec = (8 * 1000 / (128 / (CFG_CLK_DIV+1)) ) >> 1;
printk("Ralink SPI flash driver, SPI clock: %dMHz\n", (get_surfboard_sysclk() / 1000000) >> (CFG_CLK_DIV+1));
return 0;
}
static void RaWdgStart(void)
{
/*
* For user easy configuration, We assume the unit of watch dog timer is 1s,
* so we need to calculate the TMR1LOAD value.
*
* Unit= 1/(SysClk/65536), 1 Sec = (SysClk)/65536
*
*/
SetTimerMode(TMR1CTL,WATCHDOG);
SetWdgTimerClock(TMR1CTL,SYS_CLK_DIV65536);
#if defined (CONFIG_RALINK_RT2880) || defined (CONFIG_RALINK_RT2883) || \
defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3883)
WdgLoadValue = WATCHDOG_TIMEOUT * (get_surfboard_sysclk()/65536);
#elif defined (CONFIG_RALINK_RT63365)
WdgLoadValue = WATCHDOG_TIMEOUT * (25000000 / 2); //FIXME
#else
WdgLoadValue = WATCHDOG_TIMEOUT * (40000000/65536); //fixed at 40Mhz
#endif
sysRegWrite(TMR1LOAD, WdgLoadValue);
SetWdgTimerEbl(TMR1CTL,1);
printk(KERN_INFO "Started WatchDog Timer.\n");
}
static void RaWdgStart(void)
{
#if defined (CONFIG_RALINK_RT6855A)
int HwConf;
#endif
printk(KERN_INFO "Started WatchDog Timer.\n");
SetTimerMode(TMR1CTL,WATCHDOG);
#if defined (CONFIG_RALINK_RT2880) || defined (CONFIG_RALINK_RT2883) || \
defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3883)
/*
* For user easy configuration, We assume the unit of watch dog timer is 1s,
* so we need to calculate the TMR1LOAD value.
*
* Unit= 1/(SysClk/65536), 1 Sec = (SysClk)/65536
*
*/
SetWdgTimerClock(TMR1CTL,SYS_CLK_DIV65536);
WdgLoadValue = WATCHDOG_TIMEOUT * (get_surfboard_sysclk()/65536);
#elif defined (CONFIG_RALINK_RT6855A)
HwConf = sysRegRead(RALINK_SYSCTL_BASE + 0x8c);
if(((HwConf >> 24) & 0x3) == 0) { //SDR
WdgLoadValue = WATCHDOG_TIMEOUT * (140 * 1000 * 1000 / 2);
}else {
if(((HwConf >> 26) & 0x1) == 0) {
void spic_init(void)
{
u32 clk_sys, clk_div, reg;
#if defined (CONFIG_RALINK_MT7621)
clk_sys = 125; /* bclk = 125MHz */
#if defined (CONFIG_MTD_SPI_FAST_CLOCK)
clk_div = 4; /* bclk/4 -> 31.25 MHz */
#else
clk_div = 5; /* bclk/5 -> 25 MHz */
#endif
#elif defined (CONFIG_RALINK_MT7628)
clk_sys = get_surfboard_sysclk() / 1000000;
#if defined (CONFIG_MTD_SPI_FAST_CLOCK)
clk_div = 5; /* hclk/5 -> 40 MHz */
#else
clk_div = 8; /* hclk/8 -> 25 MHz */
#endif
#endif
reg = ra_inl(SPI_REG_MASTER);
reg &= ~(0x7);
reg &= ~(0x0fff << 16);
reg |= ((clk_div - 2) << 16);
ra_outl(SPI_REG_MASTER, reg);
#ifdef TEST_CS1_FLASH
#if defined (CONFIG_RALINK_MT7628)
ra_and(RALINK_REG_GPIOMODE, ~(3 << 4));
#endif
ra_or(SPI_REG_MASTER, (1 << 29));
#endif
printk("Ralink SPI flash driver, SPI clock: %dMHz\n", clk_sys / clk_div);
}
int __init ralink_wdt_init_module(void)
{
// initialize WDG timer (Timer1)
setup_timer(&wdg_timer, on_refresh_wdg_timer, 0);
set_wdg_timer_mode(TMR1CTL, WATCHDOG);
#if defined (CONFIG_RALINK_RT2880) || defined (CONFIG_RALINK_RT2883) || \
defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3883)
/*
* System Clock = CPU Clock/2
* For user easy configuration, We assume the unit of watch dog timer is 1s,
* so we need to calculate the TMR1LOAD value.
* Unit= 1/(SysClk/65536), 1 Sec = (SysClk)/65536
*/
set_wdg_timer_clock_prescale(TMR1CTL, SYS_CLK_DIV65536);
wdg_load_value = CONFIG_RALINK_TIMER_WDG_REBOOT_DELAY * (get_surfboard_sysclk() / 65536);
#elif defined (CONFIG_RALINK_MT7621)
set_wdg_timer_clock_prescale(1000); //1ms
wdg_load_value = CONFIG_RALINK_TIMER_WDG_REBOOT_DELAY * 1000;
sysRegWrite(TMR1LOAD, wdg_load_value);
#else /* RT3352/RT5350/MT7620 */
set_wdg_timer_clock_prescale(TMR1CTL, SYS_CLK_DIV65536);
wdg_load_value = CONFIG_RALINK_TIMER_WDG_REBOOT_DELAY * (40000000 / 65536);
#endif
on_refresh_wdg_timer(0);
set_wdg_timer_ebl(TMR1CTL, 1);
printk("Load Ralink WDG Timer Module\n");
return 0;
}
int request_tmr_service(int interval, void (*function)(unsigned long), unsigned long data)
{
unsigned int reg_val;
unsigned long flags;
spin_lock_irqsave(&tmr0.tmr0_lock, flags);
//Set Callback function
tmr0.data = data;
tmr0.tmr0_callback_function = function;
//Timer 0 Interrupt Status Enable
reg_val = sysRegRead(INTENA);
reg_val |= 1;
sysRegWrite(INTENA, reg_val);
//Set Timer0 Mode
set_timer_mode(TMR0CTL, PERIODIC);
//Set Period Interval
//Unit= SysClk/16384, 1ms = (SysClk/16384)/1000
set_timer_clock_prescale(TMR0CTL,SYS_CLK_DIV16384);
#if defined (CONFIG_RALINK_RT2880) || defined (CONFIG_RALINK_RT2883) || \
defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3883)
sysRegWrite(TMR0LOAD, interval* (get_surfboard_sysclk()/16384/1000));
#else //RT3352
sysRegWrite(TMR0LOAD, interval* (40000000/16384/1000)); //fixed at 40MHz
#endif
//Enable Timer0
set_dfs_timer_ebl(TMR0CTL,1);
spin_unlock_irqrestore(&tmr0.tmr0_lock, flags);
return 0;
}
/* must be spinlock protected */
static void
fe_dma_init(END_DEVICE *ei_local)
{
int i;
u32 regVal;
/* init PDMA TX ring */
for (i = 0; i < NUM_TX_DESC; i++) {
struct PDMA_txdesc *txd = &ei_local->txd_ring[i];
ei_local->txd_buff[i] = NULL;
ACCESS_ONCE(txd->txd_info1) = 0;
ACCESS_ONCE(txd->txd_info2) = TX2_DMA_DONE;
#if defined (RAETH_PDMA_V2)
ACCESS_ONCE(txd->txd_info4) = 0;
#else
ACCESS_ONCE(txd->txd_info4) = TX4_DMA_QN(3);
#endif
ACCESS_ONCE(txd->txd_info3) = 0;
}
/* init PDMA RX ring */
for (i = 0; i < NUM_RX_DESC; i++) {
struct PDMA_rxdesc *rxd = &ei_local->rxd_ring[i];
#if defined (RAETH_PDMA_V2)
ACCESS_ONCE(rxd->rxd_info1) = (u32)dma_map_single(NULL, ei_local->rxd_buff[i]->data, MAX_RX_LENGTH + NET_IP_ALIGN, DMA_FROM_DEVICE);
ACCESS_ONCE(rxd->rxd_info2) = RX2_DMA_SDL0_SET(MAX_RX_LENGTH);
#else
ACCESS_ONCE(rxd->rxd_info1) = (u32)dma_map_single(NULL, ei_local->rxd_buff[i]->data, MAX_RX_LENGTH, DMA_FROM_DEVICE);
ACCESS_ONCE(rxd->rxd_info2) = RX2_DMA_LS0;
#endif
ACCESS_ONCE(rxd->rxd_info3) = 0;
ACCESS_ONCE(rxd->rxd_info4) = 0;
}
wmb();
/* clear PDMA */
regVal = sysRegRead(PDMA_GLO_CFG);
regVal &= ~(CSR_CLKGATE | RX_DMA_EN | TX_DMA_EN);
sysRegWrite(PDMA_GLO_CFG, regVal);
/* GDMA1/2 <- TX Ring #0 */
sysRegWrite(TX_BASE_PTR0, phys_to_bus((u32)ei_local->txd_ring_phy));
sysRegWrite(TX_MAX_CNT0, cpu_to_le32(NUM_TX_DESC));
sysRegWrite(TX_CTX_IDX0, 0);
sysRegWrite(PDMA_RST_CFG, PST_DTX_IDX0);
ei_local->txd_last_idx = le32_to_cpu(sysRegRead(TX_CTX_IDX0));
ei_local->txd_free_idx = ei_local->txd_last_idx;
/* GDMA1/2 -> RX Ring #0 */
sysRegWrite(RX_BASE_PTR0, phys_to_bus((u32)ei_local->rxd_ring_phy));
sysRegWrite(RX_MAX_CNT0, cpu_to_le32(NUM_RX_DESC));
sysRegWrite(RX_CALC_IDX0, cpu_to_le32(NUM_RX_DESC - 1));
sysRegWrite(PDMA_RST_CFG, PST_DRX_IDX0);
/* only the following chipset need to set it */
#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3883)
// set 1us timer count in unit of clock cycle
regVal = sysRegRead(FE_GLO_CFG);
regVal &= ~(0xff << 8); //clear bit8-bit15
regVal |= (((get_surfboard_sysclk()/1000000)) << 8);
sysRegWrite(FE_GLO_CFG, regVal);
#endif
/* config DLY interrupt */
sysRegWrite(DLY_INT_CFG, FE_DLY_INIT_VALUE);
}
