static int read_general_5(void) {
u16 readValue;
/* Read the GENERAL5 register from the ICAP peripheral. */
putfslx(0x0FFFF, 0, FSL_CONTROL_ATOMIC);
udelay(1000);
putfslx(0x0FFFF, 0, FSL_ATOMIC); // Pad words
putfslx(0x0FFFF, 0, FSL_ATOMIC);
putfslx(0x0AA99, 0, FSL_ATOMIC); // SYNC
putfslx(0x05566, 0, FSL_ATOMIC); // SYNC
// Read GENERAL5
putfslx(0x02AE1, 0, FSL_ATOMIC);
// Add some safety noops and wait briefly
putfslx(0x02000, 0, FSL_ATOMIC); // Type 1 NOP
putfslx(0x02000, 0, FSL_ATOMIC); // Type 1 NOP
// Trigger the FSL peripheral to drain the FIFO into the ICAP.
// Wait briefly for the read to occur.
putfslx(FINISH_FSL_BIT, 0, FSL_ATOMIC);
udelay(1000);
getfslx(readValue, 0, FSL_ATOMIC); // Read the ICAP result
return readValue;
}
Hint poly_crc (void * list_ptr, Huint size)
{
Hint result = SUCCESS;
// Use Accelerator?
Hbool use_accelerator = poly_init(CRC, size);
// Start transferring data to BRAM
if(transfer_dma( (void *) list_ptr, (void *) ACC_BRAMC, size *4))
return FAILURE;
if (use_accelerator) {
int e = 0;
putfslx( size, 0, FSL_DEFAULT);//send end address
putfslx( 0, 0, FSL_DEFAULT); //send start address
getfslx(e, 0, FSL_DEFAULT);
if (e != 1) return FAILURE;
} else {
Huint vhwti_base = 0;
// Get VHWTI from PVRs
getpvr(1,vhwti_base);
hthread_time_t start = hthread_time_get();
// Run crc in software
result = (sw_crc((void *) ACC_BRAMC, size));
hthread_time_t stop = hthread_time_get();
hthread_time_t diff;
hthread_time_diff(diff, stop,start);
volatile hthread_time_t * ptr = (hthread_time_t *) (vhwti_base + 0x100);
*ptr += diff;
}
// Start transferring data from BRAM
if(transfer_dma( (void *) ACC_BRAMC, (void *) list_ptr, size *4))
return FAILURE;
return result;
}
/**
* Check to see if a Firmware update is being request, if so
* carry out firmware update and return.
*
* Returns - Zero if no firmware update was performed and no
* boot delay desired, nonzero otherwise
*
*/
int CheckFirmwareUpdate(void)
{
int doUpdate = 0;
int i;
u16 readValue;
uint32_t reqSize = sizeof(RequestMessageBuffer_t);
uint32_t respSize;
int returnValue = 0;
// Enable the mailbox.
SetupLabXMailbox();
/* Read the GENERAL5 register from the ICAP peripheral to determine
* whether the golden FPGA is still resident as the result of a re-
* configuration fallback
*/
putfslx(0x0FFFF, 0, FSL_CONTROL_ATOMIC);
udelay(1000);
/* First determine whether a reconfiguration has already been attempted
* and failed (e.g. due to a corrupted run-time bitstream). This is done
* by checking for the fallback bit in the ICAP status register.
*
* Next, examine the GPIO signal from the backplane to see if the host is
* initiating a firware update or not. If not, see if a boot delay
* is being requested by an installed jumper.
*/
putfslx(0x0FFFF, 0, FSL_ATOMIC); // Pad words
putfslx(0x0FFFF, 0, FSL_ATOMIC);
putfslx(0x0AA99, 0, FSL_ATOMIC); // SYNC
putfslx(0x05566, 0, FSL_ATOMIC); // SYNC
// Read GENERAL5
putfslx(0x02AE1, 0, FSL_ATOMIC);
// Add some safety noops and wait briefly
putfslx(0x02000, 0, FSL_ATOMIC); // Type 1 NOP
putfslx(0x02000, 0, FSL_ATOMIC); // Type 1 NOP
// Trigger the FSL peripheral to drain the FIFO into the ICAP.
// Wait briefly for the read to occur.
putfslx(FINISH_FSL_BIT, 0, FSL_ATOMIC);
udelay(1000);
getfslx(readValue, 0, FSL_ATOMIC); // Read the ICAP result
/* Check the mailbox every quarter of a second for a
total of 1 second to enter into firmware update */
for (i=0; i<4; ++i) {
if(ReadLabXMailbox(request, &reqSize, FALSE)) {
#ifdef _LABXDEBUG
printf("Length: 0x%02X\n", getLength_req(request));
printf("CC: 0x%02X\n", getClassCode_req(request));
printf("SC: 0x%02X\n", getServiceCode_req(request));
printf("AC: 0x%02X\n", getAttributeCode_req(request));
printf("Request: [ ");
for(i = 0; i < reqSize; i++) {
printf("%02X ", request[i]);
}
printf("]\n");
#endif
/* Unmarshal the received request */
switch(getClassCode_req(request)) {
case k_CC_FirmwareUpdate:
FirmwareUpdate__unmarshal(request, response);
break;
default:
// Report a malformed request
setStatusCode_resp(response, e_EC_INVALID_SERVICE_CODE);
setLength_resp(response, getPayloadOffset_resp(response));
}
respSize = getLength_resp(response);
setLength_resp(response, respSize);
WriteLabXMailbox(response, respSize);
#ifdef _LABXDEBUG
printf("Response Length: 0x%02X\n", respSize);
printf("Response Code: 0x%04X\n", getStatusCode_resp(response));
printf("Response: [ ");
for(i = 0; i < respSize; i++) {
printf("%02X ", response[i]);
}
printf("]\n");
#endif
/* Re-set the max request size for the next iteration */
reqSize = sizeof(RequestMessageBuffer_t);
/* Break out of loop, we received a valid request */
if(getStatusCode_resp(response) == e_EC_SUCCESS) break;
}
else {
udelay(250000);
}
}
if (readValue == GENERAL5_MAGIC) {
printf("Run-time FPGA reconfiguration failed\n");
doUpdate = 1;
} else if(firmwareUpdate) {
printf("Firmware Update Requested from HOST\n");
doUpdate = 1;
} else if(bootDelay) {
printf("Boot Delay Requested from HOST\n");
returnValue = 1;
} else {
printf("No Firmware update requested\n");
}
// Perform an update if required for any reason
if(doUpdate) {
printf("Entering firmware update\n");
DoFirmwareUpdate();
printf("Firmware update completed, waiting for reset from host\n");
while(1);
}
// Return, supplying a nonzero value if a boot delay was requested;
// if a firmware update was requested, we will never get here.
return(returnValue);
}
void * foo_thread(void * arg)
{
data * package = (data *) arg;
Hint * dataA = package->dataA;
Hint * dataB = package->dataB;
Hint * dataC = package->dataC;
Hint * brama = (Hint *) BRAMA;
Hint * bramb = (Hint *) BRAMB;
Hint * bramc = (Hint *) BRAMC;
int e,Status;
int time = package->time;
XTmrCtr * mytimer =package->timer;
XAxiCdma mydma;
#ifndef HETERO_COMPILATION
Status= XAxiCdma_Initialize(&mydma, XPAR_PERIPHERALS_CENTRAL_DMA_DEVICE_ID);
#else
Status= XAxiCdma_Initialize(&mydma,XPAR_GROUP_0_SLAVE_0_LOCAL_DMA_DEVICE_ID);
#endif
if (Status != XST_SUCCESS) {
putnum(0xdeadbeef);
return XST_FAILURE;
}
XAxiCdma_IntrDisable(&mydma, XAXICDMA_XR_IRQ_ALL_MASK);
XTmrCtr_Reset(mytimer,1);
//sending the data **********************************************
/*for (e = 0; e < package->vector_size; e++) {
brama[e] = dataA[e];
bramb[e] = dataB[e]; }
*/
Status = XAxiCdma_Transfer(&mydma, (u32) package->dataA , (u32) BRAMA, package->vector_size *4, NULL, NULL);
Status = XAxiCdma_Transfer(&mydma, (u32) package->dataB , (u32) BRAMB, package->vector_size *4, NULL, NULL);
//computation
// for (e = 0; e < package->vector_size; e++) bramc[e] = brama[e] + bramb[e];
/*
int cmd =1; //1=> means add, 2=> means subtraction
int start =0;
int end = package->vector_size ;
putfslx( cmd, 0, FSL_DEFAULT);
putfslx( end, 0, FSL_DEFAULT);
putfslx( start, 0, FSL_DEFAULT);
getfslx(cmd, 0, FSL_DEFAULT);
*/
putfslx((0 << 30) | (SIZE << 15) | 0, 0, FSL_DEFAULT);
getfslx(e, 0, FSL_DEFAULT);
//sending the data back to dram **********************************************
Status = XAxiCdma_Transfer(&mydma, (u32) BRAMC , (u32) package->dataC, package->vector_size *4, NULL, NULL);
// for (e = 0; e < package->vector_size; e++) dataC[e] = bramc[e];
package->time= XTmrCtr_GetValue(mytimer,1);
return (void *) 0;
}
