/*-----------------------------------------------------------------------------
* gfx_vga_seq_reset
*
* This routine enables or disables SoftVGA. It is used to make SoftVGA
* "be quiet" and not interfere with any of the direct hardware access from
* Durango. For VSA1, the sequencer is reset to stop text redraws. VSA2 may
* provide a better way to have SoftVGA sit in the background.
*-----------------------------------------------------------------------------
*/
int
gu2_vga_seq_reset(int reset)
{
gfx_outb(0x3C4, 0);
gfx_outb(0x3C5, (unsigned char)(reset ? 0x00 : 0x03));
return (GFX_STATUS_OK);
}
void
gu2_gfx_to_vga(int vga_mode)
{
int tmp;
char sequencer;
gu2_vga_extcrtc(0x40, vga_mode);
/* clear the display blanking bit */
gfx_outb(MDC_SEQUENCER_INDEX, MDC_SEQUENCER_CLK_MODE);
sequencer = gfx_inb(MDC_SEQUENCER_DATA);
sequencer &= ~MDC_CLK_MODE_SCREEN_OFF;
sequencer |= 1;
gfx_outb(MDC_SEQUENCER_DATA, sequencer);
gfx_delay_milliseconds(1);
/*restart the sequencer */
gfx_outw(0x3C4, 0x300);
/* turn on the attribute controler */
tmp = gfx_inb(0x3DA);
gfx_outb(0x3C0, 0x20);
tmp = gfx_inb(0x3DA);
gu2_vga_extcrtc(0x3F, 0);
}
/*-----------------------------------------------------------------
* Pnl_IsPanelEnabledInBIOS
*
* Description: This function specifies whether the panel is enabled
* by the BIOS or not.
* parameters: none.
* return: 1 - Enabled, 0 - Disabled
*-----------------------------------------------------------------*/
int
Pnl_IsPanelEnabledInBIOS(void)
{
unsigned char ret = 0;
if ((gfx_cpu_version & 0xFF) == GFX_CPU_REDCLOUD) {
unsigned short data;
gfx_outw(VR_INDEX, VR_UNLOCK);
gfx_outw(VR_INDEX, (VRC_VG << 8) | VG_MEM_SIZE);
data = gfx_inw(VR_DATA);
if (data & FP_DETECT_MASK)
ret = 1;
} else {
unsigned short crtcindex, crtcdata;
crtcindex = (gfx_inb(0x3CC) & 0x01) ? 0x3D4 : 0x3B4;
crtcdata = crtcindex + 1;
/* CHECK DisplayEnable Reg in SoftVGA */
gfx_outb(crtcindex, (unsigned char)SOFTVGA_DISPLAY_ENABLE);
ret = gfx_inb(crtcdata);
}
return (ret & 0x1);
}
void
gu2_vga_extcrtc(char offset, int reset)
{
unsigned short crtcindex, crtcdata;
crtcindex = (gfx_inb(0x3CC) & 0x01) ? 0x3D4 : 0x3B4;
crtcdata = crtcindex + 1;
/* UNLOCK EXTENDED CRTC REGISTERS */
gfx_outb(crtcindex, 0x30);
gfx_outb(crtcdata, 0x57);
gfx_outb(crtcdata, 0x4C);
/* RESTORE EXTENDED CRTC REGISTERS */
gfx_outb(crtcindex, offset);
gfx_outb(crtcdata, reset);
#if 0
/* LOCK EXTENDED CRTC REGISTERS */
gfx_outb(crtcindex, 0x30);
gfx_outb(crtcdata, 0x00);
#endif
}
int
gu2_vga_attr_ctrl(int reset)
{
(void) gfx_inb(0x3DA);
gfx_outb(0x3C0, (unsigned char)(reset ? 0x00 : 0x20));
if (reset)
(void) gfx_inb(0x3DA);
return (GFX_STATUS_OK);
}
int
gu2_vga_seq_blanking(void)
{
int tmp;
gfx_outb(0x3C4, 1);
tmp = gfx_inb(0x3C5);
tmp |= 0x20;
tmp |= tmp << 8;
gfx_outw(0x3C4, tmp);
gfx_delay_milliseconds(1);
return (GFX_STATUS_OK);
}
/*-----------------------------------------------------------------------------
* gfx_vga_clear_extended
*
* This routine clears the extended SoftVGA register values to have SoftVGA
* behave like standard VGA.
*-----------------------------------------------------------------------------
*/
void
gu2_vga_clear_extended(void)
{
int i;
unsigned short crtcindex, crtcdata;
crtcindex = (gfx_inb(0x3CC) & 0x01) ? 0x3D4 : 0x3B4;
crtcdata = crtcindex + 1;
gfx_outb(crtcindex, 0x30);
gfx_outb(crtcdata, 0x57);
gfx_outb(crtcdata, 0x4C);
for (i = 0x41; i <= 0x4F; i++) {
gfx_outb(crtcindex, (unsigned char)i);
gfx_outb(crtcdata, 0);
}
gfx_outb(crtcindex, 0x30);
gfx_outb(crtcdata, 0x00);
}
/*-----------------------------------------------------------------------------
* gfx_vga_restore
*
* This routine restores the state of the VGA registers from the specified
* structure. Flags indicate what portions of the register state need to
* be saved.
*-----------------------------------------------------------------------------
*/
int
gu2_vga_restore(gfx_vga_struct * vga, int flags)
{
int i;
unsigned short crtcindex, crtcdata;
crtcindex = (gfx_inb(0x3CC) & 0x01) ? 0x3D4 : 0x3B4;
crtcdata = crtcindex + 1;
/* CHECK MISCELLANEOUS OUTPUT FLAG */
if (flags & GU2_VGA_FLAG_MISC_OUTPUT) {
/* RESTORE MISCELLANEOUS OUTPUT REGISTER VALUE */
gfx_outb(0x3C2, vga->miscOutput);
}
/* CHECK SEQ */
if (flags & GU2_VGA_FLAG_SEQ) {
/* RESTORE STANDARD CRTC REGISTERS */
for (i = 1; i < GU2_SEQ_REGS; i++) {
gfx_outb(0x3C4, (unsigned char)i);
gfx_outb(0x3C5, SEQregs[i]);
}
}
/* CHECK STANDARD CRTC FLAG */
if (flags & GU2_VGA_FLAG_STD_CRTC) {
/* UNLOCK STANDARD CRTC REGISTERS */
gfx_outb(crtcindex, 0x11);
gfx_outb(crtcdata, 0);
/* RESTORE STANDARD CRTC REGISTERS */
for (i = 0; i < GU2_STD_CRTC_REGS; i++) {
gfx_outb(crtcindex, (unsigned char)i);
gfx_outb(crtcdata, vga->stdCRTCregs[i]);
}
}
/* CHECK GDC */
if (flags & GU2_VGA_FLAG_GDC) {
/* SAVE STANDARD CRTC REGISTERS */
for (i = 0; i < GU2_GDC_REGS; i++) {
gfx_outb(0x3CE, (unsigned char)i);
gfx_outb(0x3CF, GDCregs[i]);
}
}
/* CHECK EXTENDED CRTC FLAG */
if (flags & GU2_VGA_FLAG_EXT_CRTC) {
/* UNLOCK EXTENDED CRTC REGISTERS */
gfx_outb(crtcindex, 0x30);
gfx_outb(crtcdata, 0x57);
gfx_outb(crtcdata, 0x4C);
/* RESTORE EXTENDED CRTC REGISTERS */
for (i = 1; i < GU2_EXT_CRTC_REGS; i++) {
gfx_outb(crtcindex, (unsigned char)(0x40 + i));
gfx_outb(crtcdata, vga->extCRTCregs[i]);
}
/* LOCK EXTENDED CRTC REGISTERS */
gfx_outb(crtcindex, 0x30);
gfx_outb(crtcdata, 0x00);
/* CHECK IF DIRECT FRAME BUFFER MODE (VESA MODE) */
if (vga->extCRTCregs[0x03] & 1) {
/* SET BORDER COLOR TO BLACK */
/* This really should be another thing saved/restored, but */
/* Durango currently doesn't do the attr controller registers. */
gfx_inb(0x3BA); /* Reset flip-flop */
gfx_inb(0x3DA);
gfx_outb(0x3C0, 0x11);
gfx_outb(0x3C0, 0x00);
}
}
if (flags & GU2_VGA_FLAG_PALETTE) {
/* RESTORE PALETTE DATA */
for (i = 0; i < 0x100; i++) {
gfx_outb(0x3C8, i);
gfx_outb(0x3C9, palette[i]);
}
}
if (flags & GU2_VGA_FLAG_ATTR) {
/* RESTORE Attribute DATA */
for (i = 0; i < 21; i++) {
gfx_inb(0x3DA);
gfx_outb(0x3C0, i);
gfx_outb(0x3C0, ATTRregs[i]);
}
/* SAVE Attribute DATA */
for (i = 0; i < 21; i++) {
gfx_inb(0x3DA);
gfx_outb(0x3C0, i);
}
}
/* restore the VGA data */
gu2_vga_font_data(1);
return (0);
}
/*-----------------------------------------------------------------------------
* gfx_vga_save
*
* This routine saves the state of the VGA registers into the specified
* structure. Flags indicate what portions of the register state need to
* be saved.
*-----------------------------------------------------------------------------
*/
int
gu2_vga_save(gfx_vga_struct * vga, int flags)
{
int i;
unsigned short crtcindex, crtcdata;
crtcindex = (gfx_inb(0x3CC) & 0x01) ? 0x3D4 : 0x3B4;
crtcdata = crtcindex + 1;
/* CHECK MISCELLANEOUS OUTPUT FLAG */
if (flags & GU2_VGA_FLAG_MISC_OUTPUT) {
/* SAVE MISCCELLANEOUS OUTPUT REGISTER */
vga->miscOutput = gfx_inb(0x3CC);
}
/* CHECK SEQ */
if (flags & GU2_VGA_FLAG_SEQ) {
/* SAVE STANDARD CRTC REGISTERS */
for (i = 1; i < GU2_SEQ_REGS; i++) {
gfx_outb(0x3C4, (unsigned char)i);
SEQregs[i] = gfx_inb(0x3C5);
}
}
/* CHECK STANDARD CRTC FLAG */
if (flags & GU2_VGA_FLAG_STD_CRTC) {
/* SAVE STANDARD CRTC REGISTERS */
for (i = 0; i < GU2_STD_CRTC_REGS; i++) {
gfx_outb(crtcindex, (unsigned char)i);
vga->stdCRTCregs[i] = gfx_inb(crtcdata);
}
}
/* CHECK GDC */
if (flags & GU2_VGA_FLAG_GDC) {
/* SAVE STANDARD CRTC REGISTERS */
for (i = 0; i < GU2_GDC_REGS; i++) {
gfx_outb(0x3CE, (unsigned char)i);
GDCregs[i] = gfx_inb(0x3CF);
}
}
/* CHECK EXTENDED CRTC FLAG */
if (flags & GU2_VGA_FLAG_EXT_CRTC) {
/* SAVE EXTENDED CRTC REGISTERS */
for (i = 0; i < GU2_EXT_CRTC_REGS; i++) {
gfx_outb(crtcindex, (unsigned char)(0x40 + i));
vga->extCRTCregs[i] = gfx_inb(crtcdata);
}
}
if (flags & GU2_VGA_FLAG_PALETTE) {
/* SAVE PALETTE DATA */
for (i = 0; i < 0x100; i++) {
gfx_outb(0x3C7, i);
palette[i] = gfx_inb(0x3C9);
}
}
if (flags & GU2_VGA_FLAG_ATTR) {
/* SAVE Attribute DATA */
for (i = 0; i < 21; i++) {
gfx_inb(0x3DA);
gfx_outb(0x3C0, i);
ATTRregs[i] = gfx_inb(0x3C1);
}
}
/* save the VGA data */
gu2_vga_font_data(0);
return (0);
}
/*-----------------------------------------------------------------
* Pnl_GetPanelInfoFromBIOS
*
* Description: This function queries the panel information from
* the BIOS.
* parameters:
* xres: width of the panel configured
* yres: height of the panel configured
* bpp: depth of the panel configured
* hz: vertical frequency of the panel configured
* return: none
*-----------------------------------------------------------------*/
void
Pnl_GetPanelInfoFromBIOS(int *xres, int *yres, int *bpp, int *hz)
{
unsigned short crtcindex, crtcdata;
unsigned short ret;
if ((gfx_cpu_version & 0xFF) == GFX_CPU_REDCLOUD) {
gfx_outw(VR_INDEX, VR_UNLOCK);
gfx_outw(VR_INDEX, (VRC_VG << 8) | VG_FP_TYPE);
ret = gfx_inw(VR_DATA);
switch (ret & FP_RESOLUTION_MASK) {
case FP_RES_6X4:
*xres = 640;
*yres = 480;
break;
case FP_RES_8X6:
*xres = 800;
*yres = 600;
break;
case FP_RES_10X7:
*xres = 1024;
*yres = 768;
break;
case FP_RES_12X10:
*xres = 1280;
*yres = 1024;
break;
case FP_RES_16X12:
*xres = 1600;
*yres = 1200;
break;
}
switch (ret & FP_WIDTH_MASK) {
case FP_WIDTH_8:
*bpp = 8;
break;
case FP_WIDTH_9:
*bpp = 9;
break;
case FP_WIDTH_12:
*bpp = 12;
break;
case FP_WIDTH_18:
*bpp = 18;
break;
case FP_WIDTH_24:
*bpp = 24;
break;
case FP_WIDTH_16:
*bpp = 16;
break;
}
switch (ret & FP_REF_MASK) {
case FP_REF_60:
*hz = 60;
break;
case FP_REF_65:
*hz = 65;
break;
case FP_REF_70:
*hz = 70;
break;
case FP_REF_72:
*hz = 72;
break;
case FP_REF_75:
*hz = 75;
break;
case FP_REF_85:
*hz = 85;
break;
}
} else {
crtcindex = (gfx_inb(0x3CC) & 0x01) ? 0x3D4 : 0x3B4;
crtcdata = crtcindex + 1;
/* CHECK FPResolution Reg in SoftVGA */
gfx_outb(crtcindex, (unsigned char)SOFTVGA_FPRESOLUTION);
ret = gfx_inb(crtcdata);
switch (ret & 0x3) {
case 0:
*xres = 640;
*yres = 480;
break;
case 1:
*xres = 800;
*yres = 600;
break;
case 2:
*xres = 1024;
*yres = 768;
break;
}
switch ((ret >> 4) & 0x3) {
case 0:
*bpp = 12;
break;
case 1:
*bpp = 18;
break;
case 2:
*bpp = 16;
break;
case 3:
*bpp = 8;
break;
}
/* CHECK FPClockFrequency Reg in SoftVGA */
gfx_outb(crtcindex, (unsigned char)SOFTVGA_FPCLOCKFREQUENCY);
*hz = gfx_inb(crtcdata);
}
}
