//************************************************************************************************
// FIQ handler for FIQ when in NWd
uint64_t tbase_fiq_handler( uint32_t id,
uint32_t flags,
void *handle,
void *cookie)
{
uint64_t mpidr;
uint32_t linear_id;
tbase_context *tbase_ctx;
mpidr = read_mpidr();
linear_id = platform_get_core_pos(mpidr);
tbase_ctx = &secure_context[linear_id];
assert(&tbase_ctx->cpu_ctx == cm_get_context(SECURE));
/* Check if the vector has been entered for SGI/FIQ dump reason */
if (id == FIQ_SMP_CALL_SGI) {
/* ACK gic */
{
unsigned int iar;
iar = gicc_read_IAR(get_plat_config()->gicc_base);
gicc_write_EOIR(get_plat_config()->gicc_base, iar);
}
/* Save the non-secure context before entering the TSP */
cm_el1_sysregs_context_save(NON_SECURE);
/* Call customer's dump implementation */
plat_tbase_dump();
// Load NWd
//cm_el1_sysregs_context_restore(NON_SECURE);
//cm_set_next_eret_context(NON_SECURE);
}
else {
/* Check the security state when the exception was generated */
assert(get_interrupt_src_ss(flags) == NON_SECURE);
/* Sanity check the pointer to this cpu's context */
assert(handle == cm_get_context(NON_SECURE));
if ((tbaseExecutionStatus&TBASE_STATUS_SMC_OK_BIT)==0) {
// TBASE must be initialized to be usable
// TODO: What should we really do here?
// We should disable FIQs to prevent futher interrupts
DBG_PRINTF( "tbase_interrupt_handler tbase not ready for interrupt\n\r" );
return 1;
}
if(tbase_ctx->state == TBASE_STATE_OFF) {
DBG_PRINTF( "tbase_interrupt_handler tbase not ready for fastcall\n\r" );
return 1;
}
/* Save the non-secure context before entering the TSP */
cm_el1_sysregs_context_save(NON_SECURE);
/* Switch to secure context now */
cm_el1_sysregs_context_restore(SECURE);
cm_set_next_eret_context(SECURE);
// Load SWd context
tbase_setup_entry_nwd((cpu_context_t *)handle,ENTRY_OFFSET_FIQ);
// Enter tbase. tbase must return using normal SMC, which will continue here.
tbase_synchronous_sp_entry(tbase_ctx);
// Load NWd
cm_el1_sysregs_context_restore(NON_SECURE);
cm_set_next_eret_context(NON_SECURE);
}
return 0;
}
/*******************************************************************************
* This functions writes the GIC cpu interface End Of Interrupt register with
* the passed value to finish handling the active interrupt
******************************************************************************/
void plat_ic_end_of_interrupt(uint32_t id)
{
gicc_write_EOIR(GICC_BASE, id);
}
/*******************************************************************************
* This functions writes the GIC cpu interface End Of Interrupt register with
* the passed value to finish handling the active interrupt
******************************************************************************/
void tegra_gic_end_of_interrupt(uint32_t id)
{
gicc_write_EOIR(TEGRA_GICC_BASE, id);
}
