/******************************************************************************* * Enable secure interrupts and set the priority mask register to allow all * interrupts to trickle in. ******************************************************************************/ static void tegra_gic_cpuif_setup(unsigned int gicc_base) { unsigned int val; val = ENABLE_GRP0 | ENABLE_GRP1 | FIQ_EN | FIQ_BYP_DIS_GRP0; val |= IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1; gicc_write_ctlr(gicc_base, val); gicc_write_pmr(gicc_base, GIC_PRI_MASK); }
/******************************************************************************* * Enable secure interrupts and use FIQs to route them. Disable legacy bypass * and set the priority mask register to allow all interrupts to trickle in. ******************************************************************************/ void gic_cpuif_setup(unsigned int gicc_base) { unsigned int val; gicc_write_pmr(gicc_base, GIC_PRI_MASK); val = ENABLE_GRP0 | FIQ_EN; val |= FIQ_BYP_DIS_GRP0 | IRQ_BYP_DIS_GRP0; val |= FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1; gicc_write_ctlr(gicc_base, val); }
/******************************************************************************* * Enable secure interrupts and set the priority mask register to allow all * interrupts to trickle in. ******************************************************************************/ static void tegra_gic_cpuif_setup(unsigned int gicc_base) { gicc_write_ctlr(gicc_base, ENABLE_GRP0 | ENABLE_GRP1); gicc_write_pmr(gicc_base, GIC_PRI_MASK); }