/******************************************************************************* * Global gic distributor setup which will be done by the primary cpu after a * cold boot. It marks out the non secure SPIs, PPIs & SGIs and enables them. * It then enables the secure GIC distributor interface. ******************************************************************************/ static void tegra_gic_distif_setup(unsigned int gicd_base) { unsigned int index, num_ints; /* * Mark out non-secure interrupts. Calculate number of * IGROUPR registers to consider. Will be equal to the * number of IT_LINES */ num_ints = gicd_read_typer(gicd_base) & IT_LINES_NO_MASK; num_ints = (num_ints + 1) << 5; for (index = MIN_SPI_ID; index < num_ints; index += 32) gicd_write_igroupr(gicd_base, index, ~0); /* Setup SPI priorities doing four at a time */ for (index = MIN_SPI_ID; index < num_ints; index += 4) { gicd_write_ipriorityr(gicd_base, index, GICD_IPRIORITYR_DEF_VAL); } /* * Configure the SGI and PPI. This is done in a separated function * because each CPU is responsible for initializing its own private * interrupts. */ tegra_gic_pcpu_distif_setup(gicd_base); /* enable distributor */ gicd_write_ctlr(gicd_base, ENABLE_GRP0 | ENABLE_GRP1); }
/******************************************************************************* * Global gic distributor setup which will be done by the primary cpu after a * cold boot. It marks out the secure SPIs, PPIs & SGIs and enables them. It * then enables the secure GIC distributor interface. ******************************************************************************/ static void gic_distif_setup(unsigned int gicd_base) { unsigned int i, ctlr; const unsigned int ITLinesNumber = gicd_read_typer(gicd_base) & IT_LINES_NO_MASK; /* Disable the distributor before going further */ ctlr = gicd_read_ctlr(gicd_base); ctlr &= ~(ENABLE_GRP0 | ENABLE_GRP1); gicd_write_ctlr(gicd_base, ctlr); /* Mark all lines of SPIs as Group 1 (non-secure) */ for (i = 0; i < ITLinesNumber; i++) mmio_write_32(gicd_base + GICD_IGROUPR + 4 + i * 4, 0xffffffffu); /* Setup SPI priorities doing four at a time */ for (i = 0; i < ITLinesNumber * 32; i += 4) mmio_write_32(gicd_base + GICD_IPRIORITYR + 32 + i, DEFAULT_NS_PRIORITY_X4); /* Configure the SPIs we want as secure */ static const char sec_irq[] = { IRQ_MHU, IRQ_GPU_SMMU_0, IRQ_GPU_SMMU_1, IRQ_ETR_SMMU, IRQ_TZC400, IRQ_TZ_WDOG }; for (i = 0; i < sizeof(sec_irq) / sizeof(sec_irq[0]); i++) gic_set_secure(gicd_base, sec_irq[i]); /* Route watchdog interrupt to this CPU and enable it. */ gicd_set_itargetsr(gicd_base, IRQ_TZ_WDOG, platform_get_core_pos(read_mpidr())); gicd_set_isenabler(gicd_base, IRQ_TZ_WDOG); /* Now setup the PPIs */ gic_pcpu_distif_setup(gicd_base); /* Enable Group 0 (secure) interrupts */ gicd_write_ctlr(gicd_base, ctlr | ENABLE_GRP0); }
/******************************************************************************* * Global gic distributor setup which will be done by the primary cpu after a * cold boot. It marks out the non secure SPIs, PPIs & SGIs and enables them. * It then enables the secure GIC distributor interface. ******************************************************************************/ static void tegra_gic_distif_setup(unsigned int gicd_base) { unsigned int ctr, num_ints; /* * Mark out non-secure interrupts. Calculate number of * IGROUPR registers to consider. Will be equal to the * number of IT_LINES */ num_ints = gicd_read_typer(gicd_base) & IT_LINES_NO_MASK; num_ints++; for (ctr = 0; ctr < num_ints; ctr++) gicd_write_igroupr(gicd_base, ctr << IGROUPR_SHIFT, ~0); /* enable distributor */ gicd_write_ctlr(gicd_base, ENABLE_GRP0 | ENABLE_GRP1); }