/******************************************************************************* * STM32MP1 handler called when a power domain is about to be turned on. The * mpidr determines the CPU to be turned on. * call by core 0 to activate core 1 ******************************************************************************/ static int stm32_pwr_domain_on(u_register_t mpidr) { unsigned long current_cpu_mpidr = read_mpidr_el1(); uint32_t bkpr_core1_addr = tamp_bkpr(BOOT_API_CORE1_BRANCH_ADDRESS_TAMP_BCK_REG_IDX); uint32_t bkpr_core1_magic = tamp_bkpr(BOOT_API_CORE1_MAGIC_NUMBER_TAMP_BCK_REG_IDX); if (mpidr == current_cpu_mpidr) { return PSCI_E_INVALID_PARAMS; } if ((stm32_sec_entrypoint < STM32MP_SYSRAM_BASE) || (stm32_sec_entrypoint > (STM32MP_SYSRAM_BASE + (STM32MP_SYSRAM_SIZE - 1)))) { return PSCI_E_INVALID_ADDRESS; } stm32mp_clk_enable(RTCAPB); cntfrq_core0 = read_cntfrq_el0(); /* Write entrypoint in backup RAM register */ mmio_write_32(bkpr_core1_addr, stm32_sec_entrypoint); /* Write magic number in backup register */ mmio_write_32(bkpr_core1_magic, BOOT_API_A7_CORE1_MAGIC_NUMBER); stm32mp_clk_disable(RTCAPB); /* Generate an IT to core 1 */ gicv2_raise_sgi(ARM_IRQ_SEC_SGI_0, STM32MP_SECONDARY_CPU); return PSCI_E_SUCCESS; }
void plat_ic_raise_el3_sgi(int sgi_num, u_register_t target) { #if GICV2_G0_FOR_EL3 int id; /* Target must be a valid MPIDR in the system */ id = plat_core_pos_by_mpidr(target); assert(id >= 0); /* Verify that this is a secure SGI */ assert(plat_ic_get_interrupt_type(sgi_num) == INTR_TYPE_EL3); gicv2_raise_sgi(sgi_num, id); #else assert(false); #endif }