/**
* Get configuration parameters from GPBR
*/
static uint8_t load_config(void)
{
uint32_t uc_gpbr_value;
uint8_t uc_start_mode;
uc_gpbr_value = gpbr_read(GPBR0);
uc_start_mode = uc_gpbr_value & 0x0F;
if ((uc_start_mode == PHY_APP_CMD_MENU_START_MODE) || \
(uc_start_mode == PHY_APP_CMD_TX_START_MODE)) {
xAppPhyCfgTx.uc_coupling = (uc_gpbr_value >> 4) & 0xFF;
xAppPhyCfgTx.uc_channel = (uc_gpbr_value >> 12) & 0x0F;
xAppPhyCfgTx.xPhyMsg.uc_buff_id = (uc_gpbr_value >> 16) & 0x0F;
xAppPhyCfgTx.xPhyMsg.att_level = (uc_gpbr_value >> 20) & 0x1F;
xAppPhyCfgTx.xPhyMsg.scheme = (uc_gpbr_value >> 25) & 0x07;
xAppPhyCfgTx.xPhyMsg.disable_rx = (uc_gpbr_value >> 28) & 0x01;
xAppPhyCfgTx.xPhyMsg.mode = (uc_gpbr_value >> 29) & 0x07;
xAppPhyCfgTx.ul_tx_period = gpbr_read(GPBR1);
uc_gpbr_value = gpbr_read(GPBR2);
xAppPhyCfgTx.xPhyMsg.data_len = uc_gpbr_value & 0xFFFF;
xAppPhyCfgTx.uc_autodetect = (uc_gpbr_value >> 16) & 0x0F;
xAppPhyCfgTx.uc_impedance = (uc_gpbr_value >> 20) & 0x0F;
/* upload the content of data message from flash memroy */
memcpy(ucv_tx_data_buffer, (uint8_t *)ADDR_APP_PHY_MESSAGE_DATA, \
xAppPhyCfgTx.xPhyMsg.data_len );
} else {
/**
* \brief Display test core menu.
*/
static void display_menu_core(void)
{
printf("\n\r");
printf("===============================================\n\r");
printf("Menu: press a key to continue.\n\r");
printf("===============================================\n\r");
printf("Configure:\n\r");
printf(" F : 128-bit flash access\n\r");
printf(" G : 64-bit flash access\n\r");
printf("Mode:\n\r");
printf(" A : Active Mode\n\r");
#if (!SAMG)
printf(" S : Sleep Mode\n\r");
#endif
printf(" W : Wait Mode\n\r");
#if (!SAMG)
printf(" B : Backup Mode(Entered %d times).\n\r", (int)gpbr_read(GPBR0));
#endif
printf("Quit:\n\r");
printf(" Q : Quit test.\n\r");
printf("\n\r");
printf("-----------------------------------------------\n\r");
printf("Current configuration:\n\r");
printf(" CPU Clock : MCK=%d Hz\n\r", (int)g_ul_current_mck);
if ((efc_get_flash_access_mode(EFC) & EEFC_FMR_FAM) == EEFC_FMR_FAM) {
printf(" Flash access mode : 64-bit\n\r");
} else {
printf(" Flash access mode : 128-bit\n\r");
}
printf("-----------------------------------------------\n\r");
printf("\n\r");
}
/**
* \brief Test backup mode.
*
* \note To test backup mode, the program must run out of flash.
*/
static void test_backup_mode(void)
{
puts(STRING_BACKUP);
/* Wait for the transmission done before changing clock */
while (!uart_is_tx_empty(CONSOLE_UART)) {
}
/* GPBR0 is for recording times of entering into backup mode */
gpbr_write(GPBR0, gpbr_read(GPBR0) + 1);
/* Enable the PIO for wake-up */
example_set_wakeup_from_backup_mode();
/* Switch MCK to slow clock */
pmc_switch_mck_to_sclk(PMC_MCKR_PRES_CLK_1);
/* Disable unused clock to save power */
pmc_osc_disable_xtal(0);
example_disable_pll();
/* Enter into backup mode */
pmc_enable_backupmode();
/* Note: The core will reset when exiting from backup mode. */
}
//set the relay and store the new state in
//the backup register in case of software reset
int
mon_relay(int argc, char **argv){
int state;
state = gpbr_read(GPBR_RELAY_STATE);
if(argc==1){ //print the relay state
if(state)
printf("relay [on]\n");
else
printf("relay [off]\n");
return -1;
}
if(argc!=2){
printf("relay [on|off|toggle]\n");
return -1;
}
if(strcmp(argv[1],"on")==0){
gpio_set_pin_high(RELAY_PIN);
gpbr_write(GPBR_RELAY_STATE,1);
}
else if(strcmp(argv[1],"off")==0){
gpio_set_pin_low(RELAY_PIN);
gpbr_write(GPBR_RELAY_STATE,0);
}
else if(strstr(argv[1],"toggle")==argv[1]){
gpio_toggle_pin(RELAY_PIN);
if(state==0)
state = 1;
else
state = 0;
gpbr_write(GPBR_RELAY_STATE,state);
}
else{
printf("bad argument to relay\n");
return -1;
}
return 0;
}
/**
* \brief Test GPBR read/write interfaces.
*
* \param test Current test case.
*/
static void run_gpbr_test(const struct test_case *test)
{
uint32_t ul_read_value = 0;
uint32_t ul_test_page_addr = TEST_PAGE_ADDRESS;
uint32_t *ul_back_mode_flag_addr = (uint32_t *) ul_test_page_addr;
uint32_t ul_normal_mode_flag = NORMAL_MODE_FLAG;
uint32_t ul_backup_mode_flag = BACKUP_MODE_FLAG;
uint8_t uc_write_success_flag = 1;
/* Initialize flash: 6 wait states for flash writing. */
flash_init(FLASH_ACCESS_MODE_128, FLASH_WAIT_STATE_NBR);
/* Unlock flash page. */
flash_unlock(ul_test_page_addr,
ul_test_page_addr + IFLASH_PAGE_SIZE - 1, NULL, NULL);
if ((*ul_back_mode_flag_addr) == BACKUP_MODE_FLAG) {
/* Read the data from GPBR0 */
ul_read_value = gpbr_read(GPBR0);
#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CP || SAM4CM || SAMV70 || SAMV71 || SAME70 || SAMS70)
/* Erase flag page */
flash_erase_page(ul_test_page_addr, IFLASH_ERASE_PAGES_8);
/* Clear backup mode flag */
if (flash_write(ul_test_page_addr, (uint8_t *)&ul_normal_mode_flag,
sizeof(uint32_t), 0) != FLASH_RC_OK) {
uc_write_success_flag = 0;
}
#else
/* Clear backup mode flag */
if (flash_write(ul_test_page_addr, (uint8_t *)&ul_normal_mode_flag,
sizeof(uint32_t), 1) != FLASH_RC_OK) {
uc_write_success_flag = 0;
}
#endif
/* Return test result */
test_assert_true(test, (ul_read_value == GPBR_UNIT_TEST_CONST_DATA)
&& uc_write_success_flag, "Test GPBR: GPBR write error!");
/* Clear GPBR 0 */
gpbr_write(GPBR0, 0);
return;
}
/* Write the data to the backup register 0 */
gpbr_write(GPBR0, GPBR_UNIT_TEST_CONST_DATA);
/* Enable RTT wake up */
supc_set_wakeup_mode(SUPC, SUPC_WUMR_RTTEN);
/* Configure RTT */
gpbr_test_configure_rtt();
/* Wait for RTT alarm event */
rtt_write_alarm_time(RTT, RTT_WAIT_TIME);
#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CP || SAM4CM || SAMV70 || SAMV71 || SAME70 || SAMS70)
/* Erase flag page */
if(flash_erase_page(ul_test_page_addr, IFLASH_ERASE_PAGES_8) != FLASH_RC_OK)
printf("erase page failed!\r\n");
/* Write backup mode flag */
if (flash_write(ul_test_page_addr, (uint8_t *) & ul_backup_mode_flag,
sizeof(uint32_t), 0) != FLASH_RC_OK) {
/* Flag write failed, return error */
test_assert_true(test, 0, "Test GPBR: GPBR write error!");
}
#else
/* Write backup mode flag */
if (flash_write(ul_test_page_addr, (uint8_t *) & ul_backup_mode_flag,
sizeof(uint32_t), 1) != FLASH_RC_OK) {
/* Flag write failed, return error */
test_assert_true(test, 0, "Test GPBR: GPBR write error!");
}
#endif
/* Enter backup mode */
pmc_enable_backupmode();
#if (!(SAM4S) && !(SAM4E) && !(SAM4N) && !(SAM4C) && !(SAM4CP) && !(SAM4CM) && !(SAMV70) && !(SAMV71) && !(SAME70) && !(SAMS70))
supc_enable_backup_mode(SUPC);
#endif
/* We should never reach here */
test_assert_true(test, 0, "Test GPBR: GPBR write error!");
}
/**
* \brief Application entry point for RTC tamper example.
*
* \return Unused (ANSI-C compatibility).
*/
int main(void)
{
uint32_t ul_read_value[8] = {0, 0 ,0, 0, 0, 0, 0, 0};
uint32_t ul_hour0, ul_minute0, ul_second0;
uint32_t ul_year0, ul_month0, ul_day0, ul_week0;
uint32_t ul_hour1, ul_minute1, ul_second1;
uint32_t ul_year1, ul_month1, ul_day1, ul_week1;
uint32_t tmp_src0, tmp_src1, tmp_cnt;
uint8_t uc_key;
/* Initialize the SAM system */
sysclk_init();
board_init();
/* Initialize the console uart */
configure_console();
/* Output example information */
puts(STRING_HEADER);
/* Default RTC configuration, 24-hour mode */
rtc_set_hour_mode(RTC, 0);
rtc_set_waveform(RTC, RTC_OUT_CHN, RTC_OUT_SRC);
if(rstc_get_reset_cause(RSTC) == RSTC_SR_RSTTYP_BackupReset) {
/* Read the data from GPBR0 ~ 7 */
ul_read_value[0] = gpbr_read(GPBR0);
ul_read_value[1] = gpbr_read(GPBR1);
ul_read_value[2] = gpbr_read(GPBR2);
ul_read_value[3] = gpbr_read(GPBR3);
ul_read_value[4] = gpbr_read(GPBR4);
ul_read_value[5] = gpbr_read(GPBR5);
ul_read_value[6] = gpbr_read(GPBR6);
ul_read_value[7] = gpbr_read(GPBR7);
if((ul_read_value[0] == 0) &&
(ul_read_value[1] == 0) &&
(ul_read_value[2] == 0) &&
(ul_read_value[3] == 0) &&
(ul_read_value[4] == 0) &&
(ul_read_value[5] == 0) &&
(ul_read_value[6] == 0) &&
(ul_read_value[7] == 0)) {
printf("The backup register is cleared when tamper event happen!\r\n");
} else {
printf("The backup register is not cleared when tamper event happen!\r\n");
}
/* Retrieve tamper date and time */
rtc_get_tamper_time(RTC, &ul_hour0, &ul_minute0, &ul_second0, 0);
rtc_get_tamper_date(RTC, &ul_year0, &ul_month0, &ul_day0, &ul_week0, 0);
rtc_get_tamper_time(RTC, &ul_hour1, &ul_minute1, &ul_second1, 1);
rtc_get_tamper_date(RTC, &ul_year1, &ul_month1, &ul_day1, &ul_week1, 1);
tmp_cnt = rtc_get_tamper_event_counter(RTC);
tmp_src0 = rtc_get_tamper_source(RTC, 0);
tmp_src1 = rtc_get_tamper_source(RTC, 1);
printf("The first tamper event TMP%u happen in %02u:%02u:%02u,%02u/%02u/%04u\r\n",
(unsigned int)tmp_src0, (unsigned int)ul_hour0, (unsigned int)ul_minute0,
(unsigned int)ul_second0, (unsigned int)ul_month0, (unsigned int)ul_day0,
(unsigned int)ul_year0);
printf("The last tamper event TMP%u happen in %02u:%02u:%02u,%02u/%02u/%04u\r\n",
(unsigned int)tmp_src1, (unsigned int)ul_hour1, (unsigned int)ul_minute1,
(unsigned int)ul_second1, (unsigned int)ul_month1, (unsigned int)ul_day1,
(unsigned int)ul_year1);
printf("The tamper event counter is %u \r\n", (unsigned int)tmp_cnt);
}
printf("Press any key to Enter Backup Mode!\r\n");
while (uart_read(CONSOLE_UART, &uc_key));
/* Write the data to the backup register GPBR0 ~ 7 */
gpbr_write(GPBR0, GPBR_CONST_DATA);
gpbr_write(GPBR1, GPBR_CONST_DATA);
gpbr_write(GPBR2, GPBR_CONST_DATA);
gpbr_write(GPBR3, GPBR_CONST_DATA);
gpbr_write(GPBR4, GPBR_CONST_DATA);
gpbr_write(GPBR5, GPBR_CONST_DATA);
gpbr_write(GPBR6, GPBR_CONST_DATA);
gpbr_write(GPBR7, GPBR_CONST_DATA);
/* Enable TMP0 and TMP2 low power debouncer and clear GPBR when event happen */
supc_set_wakeup_mode(SUPC, SUPC_WUMR_LPDBCEN0_ENABLE |
SUPC_WUMR_LPDBCCLR_ENABLE | SUPC_WUMR_LPDBCEN2_ENABLE |
SUPC_WUMR_LPDBC_2_RTCOUT0);
/* Enable TMP0 and TMP2 wake-up input and set input type*/
supc_set_wakeup_inputs(SUPC, SUPC_WUIR_WKUPEN0_ENABLE |
SUPC_WUIR_WKUPEN14_ENABLE,
SUPC_WUIR_WKUPT0_LOW | SUPC_WUIR_WKUPT14_LOW);
printf("Enter Backup Mode!\r\n");
printf("Please press button TMP0 or TMP2 to wake up!\r\n\r\n");
/* Ensure TX is done before enter backup mode */
while (!uart_is_tx_empty(CONSOLE_UART)) {
}
/* Enter backup mode */
pmc_enable_backupmode();
while (1) {
}
}
