static unsigned int startup_giuint(struct irq_data *data) { if (gpio_lock_as_irq(&vr41xx_gpio_chip, data->hwirq)) dev_err(vr41xx_gpio_chip.dev, "unable to lock HW IRQ %lu for IRQ\n", data->hwirq); /* Satisfy the .enable semantics by unmasking the line */ unmask_giuint_low(data); return 0; }
static unsigned int em_gio_irq_startup(struct irq_data *d) { struct em_gio_priv *p = irq_data_get_irq_chip_data(d); if (gpio_lock_as_irq(&p->gpio_chip, irqd_to_hwirq(d))) dev_err(p->gpio_chip.dev, "unable to lock HW IRQ %lu for IRQ\n", irqd_to_hwirq(d)); em_gio_irq_enable(d); return 0; }
static unsigned int intel_mid_irq_startup(struct irq_data *d) { struct intel_mid_gpio *priv = irq_data_get_irq_chip_data(d); if (gpio_lock_as_irq(&priv->chip, irqd_to_hwirq(d))) dev_err(priv->chip.dev, "unable to lock HW IRQ %lu for IRQ\n", irqd_to_hwirq(d)); intel_mid_irq_unmask(d); return 0; }
static unsigned int byt_irq_startup(struct irq_data *d) { struct byt_gpio *vg = irq_data_get_irq_chip_data(d); if (gpio_lock_as_irq(&vg->chip, irqd_to_hwirq(d))) dev_err(vg->chip.dev, "unable to lock HW IRQ %lu for IRQ\n", irqd_to_hwirq(d)); byt_irq_unmask(d); return 0; }
static int pl061_irq_reqres(struct irq_data *d) { struct pl061_gpio *chip = irq_data_get_irq_chip_data(d); if (gpio_lock_as_irq(&chip->gc, irqd_to_hwirq(d))) { dev_err(chip->gc.dev, "unable to lock HW IRQ %lu for IRQ\n", irqd_to_hwirq(d)); return -EINVAL; } return 0; }
static int em_gio_irq_reqres(struct irq_data *d) { struct em_gio_priv *p = irq_data_get_irq_chip_data(d); if (gpio_lock_as_irq(&p->gpio_chip, irqd_to_hwirq(d))) { dev_err(p->gpio_chip.dev, "unable to lock HW IRQ %lu for IRQ\n", irqd_to_hwirq(d)); return -EINVAL; } return 0; }