//intr_num only support 0-7 void gpio_intr_config(uint32 gpio_num, uint32 intr_num, GPIO_INT_TYPE intr_type) { if (intr_num >= sizeof(intr_gpio_nums)) { return; } gpio_intr_reset(intr_num, 1); intr_gpio_nums[intr_num] = gpio_num; gpio_matrix_in(0x30, intr_gpio_signals[intr_num]); gpio_matrix_in(intr_gpio_nums[intr_num], intr_gpio_signals[intr_num]); gpio_intr_init(intr_num, intr_type); gpio_intr_reset(intr_num, 0); }
void spicommon_cs_initialize(spi_host_device_t host, int cs_io_num, int cs_num, int force_gpio_matrix) { if (!force_gpio_matrix && cs_io_num == io_signal[host].spics0_native && cs_num == 0) { //The cs0s for all SPI peripherals map to pin mux source 1, so we use that instead of a define. PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[cs_io_num], 1); } else { //Use GPIO matrix PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[cs_io_num], PIN_FUNC_GPIO); gpio_matrix_out(cs_io_num, io_signal[host].spics_out[cs_num], false, false); if (cs_num == 0) gpio_matrix_in(cs_io_num, io_signal[host].spics_in, false); } }
void phy_rmii_smi_configure_pins(uint8_t mdc_gpio, uint8_t mdio_gpio) { // setup SMI MDC pin gpio_set_direction(mdc_gpio, GPIO_MODE_OUTPUT); gpio_matrix_out(mdc_gpio, EMAC_MDC_O_IDX, 0, 0); PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[mdc_gpio], PIN_FUNC_GPIO); // setup SMI MDIO pin gpio_set_direction(mdio_gpio, GPIO_MODE_INPUT_OUTPUT); gpio_matrix_out(mdio_gpio, EMAC_MDO_O_IDX, 0, 0); gpio_matrix_in(mdio_gpio, EMAC_MDI_I_IDX, 0); PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[mdio_gpio], PIN_FUNC_GPIO); }
esp_err_t rmt_set_pin(rmt_channel_t channel, rmt_mode_t mode, gpio_num_t gpio_num) { RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG); RMT_CHECK(mode < RMT_MODE_MAX, RMT_MODE_ERROR_STR, ESP_ERR_INVALID_ARG); RMT_CHECK(((GPIO_IS_VALID_GPIO(gpio_num) && (mode == RMT_MODE_RX)) || (GPIO_IS_VALID_OUTPUT_GPIO(gpio_num) && (mode == RMT_MODE_TX))), RMT_GPIO_ERROR_STR, ESP_ERR_INVALID_ARG); PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[gpio_num], 2); if(mode == RMT_MODE_TX) { gpio_set_direction(gpio_num, GPIO_MODE_OUTPUT); gpio_matrix_out(gpio_num, RMT_SIG_OUT0_IDX + channel, 0, 0); } else { gpio_set_direction(gpio_num, GPIO_MODE_INPUT); gpio_matrix_in(gpio_num, RMT_SIG_IN0_IDX + channel, 0); } return ESP_OK; }
void IRAM_ATTR pinMatrixInDetach(uint8_t signal, bool high, bool inverted) { gpio_matrix_in(high?MATRIX_DETACH_IN_LOW_HIGH:MATRIX_DETACH_IN_LOW_PIN, signal, inverted); }
void IRAM_ATTR pinMatrixInAttach(uint8_t pin, uint8_t signal, bool inverted) { gpio_matrix_in(pin, signal, inverted); }
/** * @brief EXPERIMENTAL */ void I2S::cameraMode(dma_config_t config, int desc_count, int sample_count) { ESP_LOGD(LOG_TAG, ">> cameraMode"); ESP32CPP::GPIO::setInput(config.pin_d0); ESP32CPP::GPIO::setInput(config.pin_d1); ESP32CPP::GPIO::setInput(config.pin_d2); ESP32CPP::GPIO::setInput(config.pin_d3); ESP32CPP::GPIO::setInput(config.pin_d4); ESP32CPP::GPIO::setInput(config.pin_d5); ESP32CPP::GPIO::setInput(config.pin_d6); ESP32CPP::GPIO::setInput(config.pin_d7); //ESP32CPP::GPIO::setInput(config.pin_xclk); ESP32CPP::GPIO::setInput(config.pin_vsync); ESP32CPP::GPIO::setInput(config.pin_href); ESP32CPP::GPIO::setInput(config.pin_pclk); //ESP32CPP::GPIO::setOutput(config.pin_reset); const uint32_t const_high = 0x38; gpio_matrix_in(config.pin_d0, I2S0I_DATA_IN0_IDX, false); gpio_matrix_in(config.pin_d1, I2S0I_DATA_IN1_IDX, false); gpio_matrix_in(config.pin_d2, I2S0I_DATA_IN2_IDX, false); gpio_matrix_in(config.pin_d3, I2S0I_DATA_IN3_IDX, false); gpio_matrix_in(config.pin_d4, I2S0I_DATA_IN4_IDX, false); gpio_matrix_in(config.pin_d5, I2S0I_DATA_IN5_IDX, false); gpio_matrix_in(config.pin_d6, I2S0I_DATA_IN6_IDX, false); gpio_matrix_in(config.pin_d7, I2S0I_DATA_IN7_IDX, false); gpio_matrix_in(config.pin_vsync, I2S0I_V_SYNC_IDX, true); gpio_matrix_in(config.pin_href, I2S0I_H_SYNC_IDX, false); // gpio_matrix_in(const_high, I2S0I_V_SYNC_IDX, false); // gpio_matrix_in(const_high, I2S0I_H_SYNC_IDX, false); gpio_matrix_in(const_high, I2S0I_H_ENABLE_IDX, false); gpio_matrix_in(config.pin_pclk, I2S0I_WS_IN_IDX, false); // Enable and configure I2S peripheral periph_module_enable(PERIPH_I2S0_MODULE); // Toggle some reset bits in LC_CONF register // Toggle some reset bits in CONF register // Enable slave mode (sampling clock is external) i2s_conf_reset(); // Switch on Slave mode. // I2S_CONF_REG -> I2S_RX_SLAVE_MOD // Set to 1 to enable slave mode. I2S0.conf.rx_slave_mod = 1; // Enable parallel mode // I2S_CONF2_REG -> I2S_LCD_END // Set to 1 to enable LCD mode. I2S0.conf2.lcd_en = 1; // Use HSYNC/VSYNC/HREF to control sampling // I2S_CONF2_REG -> I2S_CAMERA_EN // Set to 1 to enable camera mode. I2S0.conf2.camera_en = 1; // Configure clock divider I2S0.clkm_conf.clkm_div_a = 1; I2S0.clkm_conf.clkm_div_b = 0; I2S0.clkm_conf.clkm_div_num = 2; // I2S_FIFO_CONF_REG -> I2S_DSCR_EN // FIFO will sink data to DMA I2S0.fifo_conf.dscr_en = 1; // FIFO configuration // I2S_FIFO_CONF_REG -> RX_FIFO_MOD I2S0.fifo_conf.rx_fifo_mod = 1; // 0-3??? // I2S_FIFO_CONF_REG -> RX_FIFO_MOD_FORCE_EN I2S0.fifo_conf.rx_fifo_mod_force_en = 1; // I2S_CONF_CHAN_REG -> I2S_RX_CHAN_MOD I2S0.conf_chan.rx_chan_mod = 1; // Clear flags which are used in I2S serial mode // I2S_SAMPLE_RATE_CONF_REG -> I2S_RX_BITS_MOD I2S0.sample_rate_conf.rx_bits_mod = 0; // I2S_CONF_REG -> I2S_RX_RIGHT_FIRST I2S0.conf.rx_right_first = 0; //I2S0.conf.rx_right_first = 0; // I2S_CONF_REG -> I2S_RX_MSB_RIGHT I2S0.conf.rx_msb_right = 0; //I2S0.conf.rx_msb_right = 1; // I2S_CONF_REG -> I2S_RX_MSB_SHIFT I2S0.conf.rx_msb_shift = 0; //I2S0.conf.rx_msb_shift = 1; // I2S_CONF_REG -> I2S_RX_MSB_MONO I2S0.conf.rx_mono = 0; // I2S_CONF_REG -> I2S_RX_SHORT_SYNC I2S0.conf.rx_short_sync = 0; I2S0.timing.val = 0; ESP_LOGD(LOG_TAG, "Initializing %d descriptors", desc_count); DMABuffer* pFirst = new DMABuffer(); // TODO: POTENTIAL LEAK DMABuffer* pLast = pFirst; for (int i = 1; i < desc_count; i++) { DMABuffer* pNewDMABuffer = new DMABuffer(); // TODO: POTENTIAL LEAK pLast->setNext(pNewDMABuffer); pLast = pNewDMABuffer; } pLast->setNext(pFirst); pCurrentDMABuffer = pFirst; // I2S_RX_EOF_NUM_REG I2S0.rx_eof_num = sample_count; // I2S_IN_LINK_REG -> I2S_INLINK_ADDR I2S0.in_link.addr = (uint32_t) pFirst; // I2S_IN_LINK_REG -> I2S_INLINK_START I2S0.in_link.start = 1; I2S0.int_clr.val = I2S0.int_raw.val; I2S0.int_ena.val = 0; I2S0.int_ena.in_done = 1; // Register the interrupt handler. esp_intr_alloc( ETS_I2S0_INTR_SOURCE, ESP_INTR_FLAG_INTRDISABLED | ESP_INTR_FLAG_LEVEL1 | ESP_INTR_FLAG_IRAM, &i2s_isr, this, &i2s_intr_handle); m_dmaSemaphore.take(); // Start the interrupt handler esp_intr_enable(i2s_intr_handle); I2S0.conf.rx_start = 1; /* while(1) { m_dmaSemaphore.wait(); uint32_t dataLength = pLastDMABuffer->getLength(); ESP_LOGD(LOG_TAG, "Got a DMA buffer; length=%d", dataLength); //pLastDMABuffer->dump(); uint8_t *pData = new uint8_t[dataLength]; pLastDMABuffer->getData(pData, dataLength); GeneralUtils::hexDump(pData, dataLength); delete[] pData; m_dmaSemaphore.take(); } */ ESP_LOGD(LOG_TAG, "<< cameraMode"); }
/* Do the common stuff to hook up a SPI host to a bus defined by a bunch of GPIO pins. Feed it a host number and a bus config struct and it'll set up the GPIO matrix and enable the device. It will set is_native to 1 if the bus config can be done using the IOMUX instead of using the GPIO matrix. */ esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_config_t *bus_config, int dma_chan, int flags, bool *is_native) { bool native = true; bool use_quad = (flags & SPICOMMON_BUSFLAG_QUAD) != 0; SPI_CHECK(bus_config->mosi_io_num < 0 || GPIO_IS_VALID_OUTPUT_GPIO(bus_config->mosi_io_num), "spid pin invalid", ESP_ERR_INVALID_ARG); SPI_CHECK(bus_config->sclk_io_num < 0 || GPIO_IS_VALID_OUTPUT_GPIO(bus_config->sclk_io_num), "spiclk pin invalid", ESP_ERR_INVALID_ARG); SPI_CHECK(bus_config->miso_io_num < 0 || GPIO_IS_VALID_GPIO(bus_config->miso_io_num), "spiq pin invalid", ESP_ERR_INVALID_ARG); if (use_quad) { SPI_CHECK(bus_config->quadwp_io_num < 0 || GPIO_IS_VALID_OUTPUT_GPIO(bus_config->quadwp_io_num), "spiwp pin invalid", ESP_ERR_INVALID_ARG); SPI_CHECK(bus_config->quadhd_io_num < 0 || GPIO_IS_VALID_OUTPUT_GPIO(bus_config->quadhd_io_num), "spihd pin invalid", ESP_ERR_INVALID_ARG); } //Check if the selected pins correspond to the native pins of the peripheral if (bus_config->mosi_io_num >= 0 && bus_config->mosi_io_num != io_signal[host].spid_native) native = false; if (bus_config->miso_io_num >= 0 && bus_config->miso_io_num != io_signal[host].spiq_native) native = false; if (bus_config->sclk_io_num >= 0 && bus_config->sclk_io_num != io_signal[host].spiclk_native) native = false; if (use_quad) { if (bus_config->quadwp_io_num >= 0 && bus_config->quadwp_io_num != io_signal[host].spiwp_native) native = false; if (bus_config->quadhd_io_num >= 0 && bus_config->quadhd_io_num != io_signal[host].spihd_native) native = false; } *is_native = native; if (native) { //All SPI native pin selections resolve to 1, so we put that here instead of trying to figure //out which FUNC_GPIOx_xSPIxx to grab; they all are defined to 1 anyway. if (bus_config->mosi_io_num > 0) PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[bus_config->mosi_io_num], 1); if (bus_config->miso_io_num > 0) PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[bus_config->miso_io_num], 1); if (use_quad && bus_config->quadwp_io_num > 0) PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[bus_config->quadwp_io_num], 1); if (use_quad && bus_config->quadhd_io_num > 0) PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[bus_config->quadhd_io_num], 1); if (bus_config->sclk_io_num > 0) PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[bus_config->sclk_io_num], 1); } else { //Use GPIO if (bus_config->mosi_io_num > 0) { PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[bus_config->mosi_io_num], PIN_FUNC_GPIO); gpio_set_direction(bus_config->mosi_io_num, GPIO_MODE_INPUT_OUTPUT); gpio_matrix_out(bus_config->mosi_io_num, io_signal[host].spid_out, false, false); gpio_matrix_in(bus_config->mosi_io_num, io_signal[host].spid_in, false); } if (bus_config->miso_io_num > 0) { PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[bus_config->miso_io_num], PIN_FUNC_GPIO); gpio_set_direction(bus_config->miso_io_num, GPIO_MODE_INPUT_OUTPUT); gpio_matrix_out(bus_config->miso_io_num, io_signal[host].spiq_out, false, false); gpio_matrix_in(bus_config->miso_io_num, io_signal[host].spiq_in, false); } if (use_quad && bus_config->quadwp_io_num > 0) { PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[bus_config->quadwp_io_num], PIN_FUNC_GPIO); gpio_set_direction(bus_config->quadwp_io_num, GPIO_MODE_INPUT_OUTPUT); gpio_matrix_out(bus_config->quadwp_io_num, io_signal[host].spiwp_out, false, false); gpio_matrix_in(bus_config->quadwp_io_num, io_signal[host].spiwp_in, false); } if (use_quad && bus_config->quadhd_io_num > 0) { PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[bus_config->quadhd_io_num], PIN_FUNC_GPIO); gpio_set_direction(bus_config->quadhd_io_num, GPIO_MODE_INPUT_OUTPUT); gpio_matrix_out(bus_config->quadhd_io_num, io_signal[host].spihd_out, false, false); gpio_matrix_in(bus_config->quadhd_io_num, io_signal[host].spihd_in, false); } if (bus_config->sclk_io_num > 0) { PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[bus_config->sclk_io_num], PIN_FUNC_GPIO); gpio_set_direction(bus_config->sclk_io_num, GPIO_MODE_INPUT_OUTPUT); gpio_matrix_out(bus_config->sclk_io_num, io_signal[host].spiclk_out, false, false); gpio_matrix_in(bus_config->sclk_io_num, io_signal[host].spiclk_in, false); } } //Select DMA channel. DPORT_SET_PERI_REG_BITS(DPORT_SPI_DMA_CHAN_SEL_REG, 3, dma_chan, (host * 2)); return ESP_OK; }