int sysmon1_post_test(int flags) { if (gpio_read_in_bit(CONFIG_SYS_GPIO_SYSMON_STATUS) == 0) { /* * 3.1. GPIO62 is low * Assuming system voltage failure. */ post_log("sysmon1 Abnormal voltage detected (GPIO62)\n"); post_log("POST sysmon1 FAILED\n"); return 1; } else { post_log("sysmon1 PASSED\n"); } return 0; }
unsigned char spi_read(void) { return (unsigned char)gpio_read_in_bit(SPI_DIN_GPIO15); }
int board_early_init_f(void) { u32 sdr0_pfc1, sdr0_pfc2; u32 reg; /* PLB Write pipelining disabled. Denali Core workaround */ mtdcr(PLB4A0_ACR, 0xDE000000); mtdcr(PLB4A1_ACR, 0xDE000000); /*-------------------------------------------------------------------- * Setup the interrupt controller polarities, triggers, etc. *-------------------------------------------------------------------*/ mtdcr(UIC0SR, 0xffffffff); /* clear all. if write with 1 then the status is cleared */ mtdcr(UIC0ER, 0x00000000); /* disable all */ mtdcr(UIC0CR, 0x00000000); /* we have not critical interrupts at the moment */ mtdcr(UIC0PR, 0xFFBFF1EF); /* Adjustment of the polarity */ mtdcr(UIC0TR, 0x00000900); /* per ref-board manual */ mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */ mtdcr(UIC0SR, 0xffffffff); /* clear all */ mtdcr(UIC1SR, 0xffffffff); /* clear all */ mtdcr(UIC1ER, 0x00000000); /* disable all */ mtdcr(UIC1CR, 0x00000000); /* all non-critical */ mtdcr(UIC1PR, 0xFFFFC6A5); /* Adjustment of the polarity */ mtdcr(UIC1TR, 0x60000040); /* per ref-board manual */ mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */ mtdcr(UIC1SR, 0xffffffff); /* clear all */ mtdcr(UIC2SR, 0xffffffff); /* clear all */ mtdcr(UIC2ER, 0x00000000); /* disable all */ mtdcr(UIC2CR, 0x00000000); /* all non-critical */ mtdcr(UIC2PR, 0x27C00000); /* Adjustment of the polarity */ mtdcr(UIC2TR, 0x3C000000); /* per ref-board manual */ mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */ mtdcr(UIC2SR, 0xffffffff); /* clear all */ /* Trace Pins are disabled. SDR0_PFC0 Register */ mtsdr(SDR0_PFC0, 0x0); /* select Ethernet pins */ mfsdr(SDR0_PFC1, sdr0_pfc1); /* SMII via ZMII */ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | SDR0_PFC1_SELECT_CONFIG_6; mfsdr(SDR0_PFC2, sdr0_pfc2); sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | SDR0_PFC2_SELECT_CONFIG_6; /* enable SPI (SCP) */ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL; mtsdr(SDR0_PFC2, sdr0_pfc2); mtsdr(SDR0_PFC1, sdr0_pfc1); mtsdr(SDR0_PFC4, 0x80000000); /* PCI arbiter disabled */ /* PCI Host Configuration disbaled */ mfsdr(SDR0_PCI0, reg); reg = 0; mtsdr(SDR0_PCI0, 0x00000000 | reg); gpio_write_bit(CONFIG_SYS_GPIO_FLASH_WP, 1); #if CONFIG_POST & CONFIG_SYS_POST_BSPEC1 /* enable the LSB transmitter */ gpio_write_bit(CONFIG_SYS_GPIO_LSB_ENABLE, 1); /* enable the CAN transmitter */ gpio_write_bit(CONFIG_SYS_GPIO_CAN_ENABLE, 1); reg = 0; /* reuse as counter */ out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR, in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR) & ~CONFIG_SYS_DSPIC_TEST_MASK); while (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY) && reg++ < 1000) { udelay(1000); } if (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY)) { /* set "boot error" flag */ out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR, in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR) | CONFIG_SYS_DSPIC_TEST_MASK); } #endif /* * Reset PHY's: * The PHY's need a 2nd reset pulse, since the MDIO address is latched * upon reset, and with the first reset upon powerup, the addresses are * not latched reliable, since the IRQ line is multiplexed with an * MDIO address. A 2nd reset at this time will make sure, that the * correct address is latched. */ gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 1); gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 1); udelay(1000); gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 0); gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 0); udelay(1000); gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 1); gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 1); return 0; }
int board_early_init_f(void) { uint32_t sdr0_pfc1, sdr0_pfc2; uint32_t reg; int eth; #if defined(CONFIG_KORAT_PERMANENT) unsigned mscount; extern void korat_branch_absolute(uint32_t addr); for (mscount = 0; mscount < CONFIG_SYS_KORAT_MAN_RESET_MS; ++mscount) { udelay(1000); if (gpio_read_in_bit(CONFIG_SYS_GPIO_RESET_PRESSED_)) { /* This call does not return. */ korat_branch_absolute( CONFIG_SYS_FLASH1_TOP - 2 * CONFIG_ENV_SECT_SIZE - 4); } } korat_buzzer(1); while (!gpio_read_in_bit(CONFIG_SYS_GPIO_RESET_PRESSED_)) udelay(1000); korat_buzzer(0); #endif mtdcr(EBC0_CFGADDR, EBC0_CFG); mtdcr(EBC0_CFGDATA, 0xb8400000); /* * Setup the interrupt controller polarities, triggers, etc. */ mtdcr(UIC0SR, 0xffffffff); /* clear all */ mtdcr(UIC0ER, 0x00000000); /* disable all */ mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */ mtdcr(UIC0PR, 0xfffff7ff); /* per ref-board manual */ mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */ mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */ mtdcr(UIC0SR, 0xffffffff); /* clear all */ mtdcr(UIC1SR, 0xffffffff); /* clear all */ mtdcr(UIC1ER, 0x00000000); /* disable all */ mtdcr(UIC1CR, 0x00000000); /* all non-critical */ mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */ mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */ mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ mtdcr(UIC1SR, 0xffffffff); /* clear all */ mtdcr(UIC2SR, 0xffffffff); /* clear all */ mtdcr(UIC2ER, 0x00000000); /* disable all */ mtdcr(UIC2CR, 0x00000000); /* all non-critical */ mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */ mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */ mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */ mtdcr(UIC2SR, 0xffffffff); /* clear all */ /* * Take sim card reader and CF controller out of reset. Also enable PHY * auto-detect until board-specific PHY resets are available. */ out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x02, 0xC0); /* Configure the two Ethernet PHYs. For each PHY, configure for fiber * if the SFP module is present, and for copper if it is not present. */ for (eth = 0; eth < 2; ++eth) { if (gpio_read_in_bit(CONFIG_SYS_GPIO_SFP0_PRESENT_ + eth)) { /* SFP module not present: configure PHY for copper. */ /* Set PHY to autonegotate 10 MB, 100MB, or 1 GB */ out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x03, in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x03) | 0x06 << (4 * eth)); } else { /* SFP module present: configure PHY for fiber and enable output */ gpio_write_bit(CONFIG_SYS_GPIO_PHY0_FIBER_SEL + eth, 1); gpio_write_bit(CONFIG_SYS_GPIO_SFP0_TX_EN_ + eth, 0); } } /* enable Ethernet: set GPIO45 and GPIO46 to 1 */ gpio_write_bit(CONFIG_SYS_GPIO_PHY0_EN, 1); gpio_write_bit(CONFIG_SYS_GPIO_PHY1_EN, 1); /* Wait 1 ms, then enable Fiber signal detect to PHYs. */ udelay(1000); out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x03, in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x03) | 0x88); /* select Ethernet (and optionally IIC1) pins */ mfsdr(SDR0_PFC1, sdr0_pfc1); sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | SDR0_PFC1_SELECT_CONFIG_4; #ifdef CONFIG_I2C_MULTI_BUS sdr0_pfc1 |= ((sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL); #endif mfsdr(SDR0_PFC2, sdr0_pfc2); sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | SDR0_PFC2_SELECT_CONFIG_4; mtsdr(SDR0_PFC2, sdr0_pfc2); mtsdr(SDR0_PFC1, sdr0_pfc1); /* PCI arbiter enabled */ mfsdr(SDR0_PCI0, reg); mtsdr(SDR0_PCI0, 0x80000000 | reg); return 0; }