/* gpu power clock init */
int sec_gpu_pwr_clk_init(void)
{
int ret = -1;
gpu_voltage_marin = 0;
sec_gpu_top_clock = 480;
gpu_regulator_enable();
ret = gpu_clks_get();
if (ret) {
PVR_DPF((PVR_DBG_ERROR, "gpu_clks_get error[%d]", ret));
return ret;
}
gpu_power_init();
#if defined(CONFIG_ARM_EXYNOS5410_BUS_DEVFREQ)
pm_qos_add_request(&exynos5_g3d_cpu_qos, PM_QOS_CPU_FREQ_MIN, 0);
pm_qos_add_request(&exynos5_g3d_int_qos, PM_QOS_DEVICE_THROUGHPUT, 0);
pm_qos_add_request(&exynos5_g3d_mif_qos, PM_QOS_BUS_THROUGHPUT, 0);
#endif
return ret;
}
int gpu_control_module_init(struct kbase_device *kbdev)
{
struct exynos_context *platform = (struct exynos_context *)kbdev->platform_context;
if (!platform)
return -ENODEV;
#ifdef CONFIG_PM_RUNTIME
platform->exynos_pm_domain = gpu_get_pm_domain(kbdev);
#endif /* CONFIG_PM_RUNTIME */
pkbdev = kbdev;
if (gpu_power_init(kbdev) < 0) {
GPU_LOG(DVFS_ERROR, "failed to initialize g3d power\n");
goto out;
}
if (gpu_clock_init(kbdev) < 0) {
GPU_LOG(DVFS_ERROR, "failed to initialize g3d clock\n");
goto out;
}
#ifdef CONFIG_REGULATOR
if (gpu_regulator_init(platform) < 0) {
GPU_LOG(DVFS_ERROR, "failed to initialize g3d regulator\n");
goto regulator_init_fail;
}
#endif /* CONFIG_REGULATOR */
#ifdef CONFIG_MALI_MIDGARD_DVFS
gpu_pm_qos_command(platform, GPU_CONTROL_PM_QOS_INIT);
#endif /* CONFIG_MALI_MIDGARD_DVFS */
return 0;
#ifdef CONFIG_REGULATOR
regulator_init_fail:
gpu_regulator_disable(platform);
#endif /* CONFIG_REGULATOR */
out:
return -EPERM;
}
