void main ()
{
hBSP430halPORT b0hal = hBSP430portLookup(BSP430_PLATFORM_BUTTON0_PORT_PERIPH_HANDLE);
volatile sBSP430hplPORTIE * b0hpl;
int b0pin = iBSP430portBitPosition(BSP430_PLATFORM_BUTTON0_PORT_BIT);
vBSP430platformInitialize_ni();
(void)iBSP430consoleInitialize();
cprintf("\nbutton " __DATE__ " " __TIME__ "\n");
cprintf("There's supposed to be a button at %s.%u\n",
xBSP430portName(BSP430_PLATFORM_BUTTON0_PORT_PERIPH_HANDLE),
b0pin);
if (! b0hal) {
cprintf("Whoops, guess it's not really there\n");
return;
}
b0hpl = BSP430_PORT_HAL_GET_HPL_PORTIE(b0hal);
button_state.button_cb.next_ni = b0hal->pin_cbchain_ni[b0pin];
b0hal->pin_cbchain_ni[b0pin] = &button_state.button_cb;
b0hpl->sel &= ~BSP430_PLATFORM_BUTTON0_PORT_BIT;
b0hpl->dir &= ~BSP430_PLATFORM_BUTTON0_PORT_BIT;
#if (BSP430_PORT_SUPPORTS_REN - 0)
BSP430_PORT_HAL_SET_REN(b0hal, BSP430_PLATFORM_BUTTON0_PORT_BIT, BSP430_PORT_REN_PULL_UP);
#endif /* BSP430_PORT_SUPPORTS_REN */
if (b0hpl->in & BSP430_PLATFORM_BUTTON0_PORT_BIT) {
button_state.in_mask = BSP430_PLATFORM_BUTTON0_PORT_BIT;
b0hpl->ies |= BSP430_PLATFORM_BUTTON0_PORT_BIT;
} else {
button_state.in_mask = 0;
b0hpl->ies &= ~BSP430_PLATFORM_BUTTON0_PORT_BIT;
}
b0hpl->ifg &= ~BSP430_PLATFORM_BUTTON0_PORT_BIT;
b0hpl->ie |= BSP430_PLATFORM_BUTTON0_PORT_BIT;
cprintf("Button is configured. Try pressing it. No debouncing is done.\n");
#if ! (configBSP430_CORE_LPM_EXIT_CLEAR_GIE - 0)
cprintf("WARNING: Interrupts remain enabled after wakeup\n");
#endif /* configBSP430_CORE_LPM_EXIT_CLEAR_GIE */
vBSP430ledSet(0, 1);
while (1) {
static const char * state_str[] = { "released", "pressed" };
cprintf("Count %u, in mask 0x%02x: %s\n", button_state.count, button_state.in_mask, state_str[!button_state.in_mask]);
/* Note that we've never turned interrupts on, but
* BSP430_CORE_LPM_ENTER_NI() does so internally so the ISR can be
* executed. Whether they are cleared before returning to this
* loop depends on #configBSP430_CORE_LPM_EXIT_CLEAR_GIE. */
BSP430_CORE_LPM_ENTER_NI(LPM0_bits);
#if ! (configBSP430_CORE_LPM_EXIT_CLEAR_GIE - 0)
/* Infrastructure didn't clear this, so we should */
BSP430_CORE_DISABLE_INTERRUPT();
#endif /* configBSP430_CORE_LPM_EXIT_CLEAR_GIE */
}
}
void main ()
{
sBSP430halPORT * hh10d_port = hBSP430portLookup(APP_HH10D_PORT_PERIPH_HANDLE);
hBSP430halSERIAL i2c = hBSP430serialLookup(APP_HH10D_I2C_PERIPH_HANDLE);
int uptime_Hz;
int hh10d_offs;
int hh10d_sens;
vBSP430platformInitialize_ni();
(void)iBSP430consoleInitialize();
cprintf("\nApplication starting\n");
BSP430_CORE_DELAY_CYCLES(10000);
if (NULL == hh10d_port) {
cprintf("\nERROR: No port HAL; did you enable configBSP430_HAL_%s?\n", xBSP430portName(APP_HH10D_PORT_PERIPH_HANDLE) ?: "whatever");
return;
}
void main ()
{
int rc = 0;
/* GDO0 and GDO2 are always interrupt-capable. */
volatile sBSP430hplPORTIE * gdo0 = xBSP430hplLookupPORTIE(BSP430_RF_CC110X_GDO0_PORT_PERIPH_HANDLE);
volatile sBSP430hplPORTIE * gdo2 = xBSP430hplLookupPORTIE(BSP430_RF_CC110X_GDO2_PORT_PERIPH_HANDLE);
hBSP430halPORT hgdo1 = hBSP430portLookup(BSP430_RF_CC110X_GDO1_PORT_PERIPH_HANDLE);
hBSP430halPORT hcsn = hBSP430portLookup(BSP430_RF_CC110X_CSn_PORT_PERIPH_HANDLE);
spi = hBSP430serialLookup(BSP430_RF_CC110X_SPI_PERIPH_HANDLE);
vBSP430platformInitialize_ni();
(void)iBSP430consoleInitialize();
cprintf("\nccid " __DATE__ " " __TIME__ "\n");
cprintf("GDO0 %p at %s.%u\n", gdo0, xBSP430portName(BSP430_RF_CC110X_GDO0_PORT_PERIPH_HANDLE), iBSP430portBitPosition(BSP430_RF_CC110X_GDO0_PORT_BIT));
cprintf("GDO1 HAL %p HPL %p at %s.%u\n", hgdo1, hgdo1->hpl.any, xBSP430portName(BSP430_RF_CC110X_GDO1_PORT_PERIPH_HANDLE), iBSP430portBitPosition(BSP430_RF_CC110X_GDO1_PORT_BIT));
cprintf("GDO2 %p at %s.%u\n", gdo2, xBSP430portName(BSP430_RF_CC110X_GDO2_PORT_PERIPH_HANDLE), iBSP430portBitPosition(BSP430_RF_CC110X_GDO2_PORT_BIT));
cprintf("CSn HAL %p HPL %p at %s.%u\n", hcsn, hcsn->hpl.any, xBSP430portName(BSP430_RF_CC110X_CSn_PORT_PERIPH_HANDLE), iBSP430portBitPosition(BSP430_RF_CC110X_CSn_PORT_BIT));
cprintf("SPI %p is %s\n", spi, xBSP430serialName(BSP430_RF_CC110X_SPI_PERIPH_HANDLE));
#if BSP430_PLATFORM_PERIPHERAL_HELP
cprintf("SPI Pins: %s\n", xBSP430platformPeripheralHelp(BSP430_RF_CC110X_SPI_PERIPH_HANDLE, BSP430_PERIPHCFG_SERIAL_SPI3));
#endif /* BSP430_PLATFORM_PERIPHERAL_HELP */
cprintf(__DATE__ " " __TIME__ "\n");
/* Configure the SPI interface, but immediately put it into hold
* mode so we can check CHIP_RDYn on the MISO/GDO1 input. */
spi = hBSP430serialOpenSPI(spi, BSP430_RF_CC110X_SPI_CTL0_BYTE, 0, 0);
if (spi) {
rc = iBSP430serialSetHold_rh(spi, 1);
/* GDO1 to input, pull-up */
BSP430_PORT_HAL_HPL_DIR(hgdo1) &= ~BSP430_RF_CC110X_GDO1_PORT_BIT;
BSP430_PORT_HAL_SET_REN(hgdo1, BSP430_RF_CC110X_GDO1_PORT_BIT, BSP430_PORT_REN_PULL_UP);
}
cprintf("SPI device %p hold returned %d\n", spi, rc);
if (! spi) {
return;
}
/* Configure CSn initial high to ensure we have a falling edge when
* we first enable the radio. */
BSP430_PORT_HAL_HPL_SEL(hcsn) &= ~BSP430_RF_CC110X_CSn_PORT_BIT;
BSP430_PORT_HAL_HPL_OUT(hcsn) |= BSP430_RF_CC110X_CSn_PORT_BIT;
BSP430_PORT_HAL_HPL_DIR(hcsn) |= BSP430_RF_CC110X_CSn_PORT_BIT;
/* Now enable the radio */
BSP430_PORT_HAL_HPL_OUT(hcsn) &= ~BSP430_RF_CC110X_CSn_PORT_BIT;
/* Spin until GDO1 (CHP_RDYn) is clear indicating radio is responsive */
while (BSP430_PORT_HAL_HPL_IN(hgdo1) & BSP430_RF_CC110X_GDO1_PORT_BIT) {
cprintf("Waiting for radio ready\n");
BSP430_CORE_DELAY_CYCLES(BSP430_CLOCK_NOMINAL_MCLK_HZ);
}
/* Enable SPI */
rc = iBSP430serialSetHold_rh(spi, 0);
cprintf("Radio is up, hold release %d; sending SRES strobe\n", rc);
/* Send a reset */
do {
rc = sendStrobe(0x30);
cprintf("Strobe response %#02x\n", rc);
if (0x0F != rc) {
BSP430_CORE_DELAY_CYCLES(BSP430_CLOCK_NOMINAL_MCLK_HZ);
}
} while (0x0F != rc);
cprintf("PARTNUM response %#02x\n", readRegister(0x30));
cprintf("VERSION response %#02x\n", readRegister(0x31));
cprintf("IOCFG2 read %#02x\n", readRegister(0x00));
cprintf("IOCFG1 read %#02x\n", readRegister(0x01));
cprintf("IOCFG0 read %#02x\n", readRegister(0x02));
/* ChipCon radios consume 1.4mA when idle. That goes down to
* nominally 400 nA if the GDOs are configured to "HW to 0" and the
* chip is told to power-down on loss of CSn. On the EXP430F5438
* the RF PWR header indicates that a CC1101 is using 40 nA in this
* mode.*/
rc = writeRegister(0x00, 0x2f);
rc = writeRegister(0x01, 0x2f);
rc = writeRegister(0x02, 0x2f);
cprintf("Cleared IOCFG\n");
cprintf("IOCFG2 read %#02x\n", readRegister(0x00));
cprintf("IOCFG1 read %#02x\n", readRegister(0x01));
cprintf("IOCFG0 read %#02x\n", readRegister(0x02));
/* SPWD */
rc = sendStrobe(0x39);
cprintf("SPWD got %d\n", rc);
/* Disable SPI before removing CSn otherwise the sequence isn't
* right. */
rc = iBSP430serialSetHold_rh(spi, 1);
BSP430_PORT_HAL_HPL_OUT(hcsn) |= BSP430_RF_CC110X_CSn_PORT_BIT;
/* This gets the RF2500T power down to about 120 nA. Note:
* Purposefully enter LPM with #GIE off since we do not intend to
* wake up.*/
BSP430_CORE_LPM_ENTER(LPM3_bits);
}
void main ()
{
sBSP430halPORT * port_hal;
hBSP430halTIMER hal;
volatile sBSP430hplTIMER * hpl;
vBSP430platformInitialize_ni();
(void)iBSP430consoleInitialize();
cputchar('\n');
BSP430_CORE_DELAY_CYCLES(BSP430_CLOCK_NOMINAL_MCLK_HZ / 1000);
cprintf("\n\nsynccap " __DATE__ " " __TIME__ "\n");
cprintf("External input on %s.%u corresponds to %s.%u%c\n",
xBSP430portName(BSP430_TIMER_CCACLK_CC1_PORT_PERIPH_HANDLE),
bitToPin(BSP430_TIMER_CCACLK_CC1_PORT_BIT),
xBSP430timerName(BSP430_TIMER_CCACLK_PERIPH_HANDLE),
PORT_CCIDX,
'A' + (BSP430_TIMER_CCACLK_CC1_CCIS / CCIS0));
port_hal = hBSP430portLookup(BSP430_TIMER_CCACLK_CC1_PORT_PERIPH_HANDLE);
if (NULL == port_hal) {
cprintf("Port HAL not available\n");
return;
}
hal = hBSP430timerLookup(BSP430_TIMER_CCACLK_PERIPH_HANDLE);
if (NULL == hal) {
cprintf("Can't find timer\n");
return;
}
BSP430_PORT_HAL_HPL_DIR(port_hal) &= ~BSP430_TIMER_CCACLK_CC1_PORT_BIT;
BSP430_PORT_HAL_HPL_SEL(port_hal) |= BSP430_TIMER_CCACLK_CC1_PORT_BIT;
hpl = hal->hpl;
hpl->cctl[1] = CM_3 | BSP430_TIMER_CCACLK_CC1_CCIS | SCS | CAP | CCIE;
captured.last_cci = !!(hpl->cctl[1] & CCI);
BSP430_HAL_ISR_CALLBACK_LINK_NI(sBSP430halISRIndexedChainNode,
hal->cc_cbchain_ni[PORT_CCIDX],
captured.cb,
next_ni);
hpl->ctl = TASSEL_2 | MC_2 | TACLR | TAIE;
/* Need to enable interrupts so timer overflow events are properly
* acknowledged */
while (1) {
unsigned int ccr;
unsigned int cctl;
unsigned int count;
unsigned int errors;
int last_cci;
unsigned long event_tt;
BSP430_CORE_DISABLE_INTERRUPT();
do {
event_tt = captured.event_tt;
captured.event_tt = 0;
count = captured.count;
errors = captured.errors;
captured.count = 0;
captured.errors = 0;
last_cci = captured.last_cci;
cctl = hpl->cctl[PORT_CCIDX];
ccr = hpl->ccr[PORT_CCIDX];
hpl->cctl[PORT_CCIDX] &= ~COV;
} while (0);
BSP430_CORE_ENABLE_INTERRUPT();
cprintf("Up %lu ACLK ticks, timer %lu event %lx ccr %x cctl %04x\n"
"\tCCI %d SCCI %d COV %d ; recorded CCI %d ; count %u errors %d\n",
ulBSP430uptime(),
ulBSP430timerCounter(hal, NULL),
event_tt,
ccr,
cctl,
!!(cctl & CCI), !!(cctl & SCCI), !!(cctl & COV), last_cci, count, errors);
BSP430_CORE_DELAY_CYCLES(BSP430_CLOCK_NOMINAL_MCLK_HZ);
}
}
void main ()
{
volatile sBSP430hplTIMER * const timer_hpl = xBSP430hplLookupTIMER(BSP430_TIMER_CCACLK_PERIPH_HANDLE);
unsigned int outclk;
unsigned int last_outclk;
unsigned int cctl;
hBSP430halPORT const inclk_port_hal = hBSP430portLookup(BSP430_TIMER_CCACLK_CLK_PORT_PERIPH_HANDLE);
hBSP430halPORT const cc_port_hal = hBSP430portLookup(APP_CC_PORT_PERIPH_HANDLE);
hBSP430halPORT const outclk_port_hal = hBSP430portLookup(APP_OUTCLK_PORT_PERIPH_HANDLE);
hBSP430halPORT const trigger_port_hal = hBSP430portLookup(APP_TRIGGER_PORT_PERIPH_HANDLE);
vBSP430platformInitialize_ni();
vBSP430unittestInitialize();
cprintf("timer_scs_test: " __DATE__ " " __TIME__ "\n");
if (NULL == timer_hpl) {
cprintf("ERROR: Unable to get timer HPL access\n");
return;
}
if (NULL == inclk_port_hal) {
cprintf("ERROR: Unable to get INCLK port access\n");
return;
}
if (NULL == cc_port_hal) {
cprintf("ERROR: Unable to get CC0 port access\n");
return;
}
if (NULL == outclk_port_hal) {
cprintf("ERROR: Unable to get OUTCLK port access\n");
return;
}
if (NULL == trigger_port_hal) {
cprintf("ERROR: Unable to get TRIGGER port access\n");
return;
}
cprintf("Please connect OUTCLK at %s.%u to %s INCLK at %s.%u\n",
xBSP430portName(APP_OUTCLK_PORT_PERIPH_HANDLE),
iBSP430portBitPosition(APP_OUTCLK_PORT_BIT),
xBSP430timerName(BSP430_TIMER_CCACLK_PERIPH_HANDLE),
xBSP430portName(BSP430_TIMER_CCACLK_CLK_PORT_PERIPH_HANDLE),
iBSP430portBitPosition(BSP430_TIMER_CCACLK_CLK_PORT_BIT));
cprintf("Please connect TRIGGER at %s.%u to %s CCI0%c at %s.%u\n",
xBSP430portName(APP_TRIGGER_PORT_PERIPH_HANDLE),
iBSP430portBitPosition(APP_TRIGGER_PORT_BIT),
xBSP430timerName(BSP430_TIMER_CCACLK_PERIPH_HANDLE),
'A' + (APP_CC_CCIS / CCIS0),
xBSP430portName(APP_CC_PORT_PERIPH_HANDLE),
iBSP430portBitPosition(APP_CC_PORT_BIT));
/* OUTCLK: output low */
outclk = 0;
BSP430_PORT_HAL_HPL_OUT(outclk_port_hal) &= ~APP_OUTCLK_PORT_BIT;
BSP430_PORT_HAL_HPL_DIR(outclk_port_hal) |= APP_OUTCLK_PORT_BIT;
BSP430_PORT_HAL_HPL_SEL(outclk_port_hal) &= ~APP_OUTCLK_PORT_BIT;
/* TRIGGER: output low */
BSP430_PORT_HAL_HPL_OUT(trigger_port_hal) &= ~APP_TRIGGER_PORT_BIT;
BSP430_PORT_HAL_HPL_DIR(trigger_port_hal) |= APP_TRIGGER_PORT_BIT;
BSP430_PORT_HAL_HPL_SEL(trigger_port_hal) &= ~APP_TRIGGER_PORT_BIT;
/* INCLK: input peripheral function */
BSP430_PORT_HAL_HPL_SEL(inclk_port_hal) &= ~BSP430_TIMER_CCACLK_CLK_PORT_BIT;
BSP430_PORT_HAL_HPL_SEL(inclk_port_hal) |= BSP430_TIMER_CCACLK_CLK_PORT_BIT;
/* CC0: input peripheral function */
BSP430_PORT_HAL_HPL_DIR(cc_port_hal) &= ~APP_CC_PORT_BIT;
BSP430_PORT_HAL_HPL_SEL(cc_port_hal) |= APP_CC_PORT_BIT;
cprintf("P4: DIR %04x SEL %04x\n", P4DIR, P4SEL);
#define CLEAR_CAPTURE() do { \
timer_hpl->cctl[APP_CCIDX] &= ~CCIFG; \
timer_hpl->ccr[APP_CCIDX] = 0; \
} while (0)
#define ASSERT_CLOCK_HIGH() do { \
BSP430_UNITTEST_ASSERT_TRUE(BSP430_PORT_HAL_HPL_OUT(outclk_port_hal) & APP_OUTCLK_PORT_BIT); \
} while (0)
#define ASSERT_CLOCK_LOW() do { \
BSP430_UNITTEST_ASSERT_FALSE(BSP430_PORT_HAL_HPL_OUT(outclk_port_hal) & APP_OUTCLK_PORT_BIT); \
} while (0)
#define ASSERT_CCI_HIGH() do { \
BSP430_UNITTEST_ASSERT_TRUE(CCI & timer_hpl->cctl[APP_CCIDX]); \
} while (0)
#define ASSERT_CCI_LOW() do { \
BSP430_UNITTEST_ASSERT_FALSE(CCI & timer_hpl->cctl[APP_CCIDX]); \
} while (0)
#define ASSERT_INTERNAL_TRIGGER_HIGH() do { \
BSP430_UNITTEST_ASSERT_TRUE(CCIS_3 == (CCIS_3 & timer_hpl->cctl[APP_CCIDX])); \
} while (0)
#define ASSERT_INTERNAL_TRIGGER_LOW() do { \
BSP430_UNITTEST_ASSERT_TRUE(CCIS_2 == (CCIS_3 & timer_hpl->cctl[APP_CCIDX])); \
} while (0)
#define ASSERT_NO_CAPTURE() do { \
BSP430_UNITTEST_ASSERT_FALSE(CCIFG & timer_hpl->cctl[APP_CCIDX]); \
BSP430_UNITTEST_ASSERT_EQUAL_FMTx(0, timer_hpl->ccr[APP_CCIDX]); \
} while (0)
#define ASSERT_YES_CAPTURE() do { \
BSP430_UNITTEST_ASSERT_TRUE(CCIFG & timer_hpl->cctl[APP_CCIDX]); \
BSP430_UNITTEST_ASSERT_EQUAL_FMTx(timer_hpl->r, timer_hpl->ccr[APP_CCIDX]); \
} while (0)
/* Capture asynchronously on falling edge from TRIGGER. */
timer_hpl->ccr[APP_CCIDX] = 0;
timer_hpl->cctl[APP_CCIDX] = CM_2 | APP_CC_CCIS | SCCI | CAP;
timer_hpl->cctl[APP_CCIDX] = CM_3 | APP_CC_CCIS | SCCI | CAP;
cprintf("%u: Timer: R %04x CTL %04x CCR %04x CCTL %04x\n", __LINE__, timer_hpl->r, timer_hpl->ctl, timer_hpl->ccr[APP_CCIDX], timer_hpl->cctl[APP_CCIDX]);
/* Count upwards. */
timer_hpl->ctl = TASSEL_0 | MC_2 | TACLR;
/* Validate that we can control the clock input. */
BSP430_UNITTEST_ASSERT_EQUAL_FMTx(outclk, timer_hpl->r);
BSP430_UNITTEST_ASSERT_EQUAL_FMTx(outclk, 0);
ASSERT_CLOCK_LOW();
HALF_TICK_OUTCLK();
ASSERT_CLOCK_HIGH();
BSP430_UNITTEST_ASSERT_EQUAL_FMTx(outclk, 1);
BSP430_UNITTEST_ASSERT_EQUAL_FMTx(outclk, timer_hpl->r);
HALF_TICK_OUTCLK();
ASSERT_CLOCK_LOW();
BSP430_UNITTEST_ASSERT_EQUAL_FMTx(outclk, timer_hpl->r);
BSP430_UNITTEST_ASSERT_EQUAL_FMTx(outclk, 1);
HALF_TICK_OUTCLK();
ASSERT_CLOCK_HIGH();
BSP430_UNITTEST_ASSERT_EQUAL_FMTx(outclk, timer_hpl->r);
HALF_TICK_OUTCLK();
ASSERT_CLOCK_LOW();
BSP430_UNITTEST_ASSERT_EQUAL_FMTx(outclk, timer_hpl->r);
/* Verify that we can control the trigger, and that asynchronous
* captures work. */
ASSERT_NO_CAPTURE();
ASSERT_CCI_LOW();
HALF_TRIGGER();
if (CM0 & timer_hpl->cctl[APP_CCIDX]) {
ASSERT_YES_CAPTURE();
if (! (CM1 & timer_hpl->cctl[APP_CCIDX])) {
CLEAR_CAPTURE();
}
} else {
ASSERT_NO_CAPTURE();
}
ASSERT_CCI_HIGH();
HALF_TRIGGER();
ASSERT_YES_CAPTURE();
ASSERT_CCI_LOW();
CLEAR_CAPTURE();
/* Advance the clock. Make sure no capture occurred. */
last_outclk = outclk;
HALF_TICK_OUTCLK();
BSP430_UNITTEST_ASSERT_EQUAL_FMTx(outclk, last_outclk+1);
BSP430_UNITTEST_ASSERT_EQUAL_FMTx(outclk, timer_hpl->r);
ASSERT_NO_CAPTURE();
last_outclk = outclk;
HALF_TICK_OUTCLK();
BSP430_UNITTEST_ASSERT_EQUAL_FMTx(last_outclk, timer_hpl->r);
ASSERT_NO_CAPTURE();
/* Now turn on synchronous capture */
timer_hpl->cctl[APP_CCIDX] |= SCS;
/* Advance the clock. Make sure no capture occurred */
cctl = timer_hpl->cctl[APP_CCIDX];
last_outclk = outclk;
ASSERT_CLOCK_LOW();
HALF_TICK_OUTCLK();
ASSERT_CLOCK_HIGH();
ASSERT_NO_CAPTURE();
HALF_TICK_OUTCLK();
ASSERT_CLOCK_LOW();
ASSERT_NO_CAPTURE();
BSP430_UNITTEST_ASSERT_EQUAL_FMTx(last_outclk+1, timer_hpl->r);
BSP430_UNITTEST_ASSERT_EQUAL_FMTx(cctl, timer_hpl->cctl[APP_CCIDX]);
/* Do this again to make really sure no capture occurred. */
HALF_TICK_OUTCLK();
ASSERT_NO_CAPTURE();
HALF_TICK_OUTCLK();
ASSERT_NO_CAPTURE();
BSP430_UNITTEST_ASSERT_EQUAL_FMTx(last_outclk+2, timer_hpl->r);
BSP430_UNITTEST_ASSERT_EQUAL_FMTx(cctl, timer_hpl->cctl[APP_CCIDX]);
/*
F1) CCI rises then falls while CLK remains low. CCIFG remains low. When CLK
rises the counter is incremented but CCIFG remains low. CCIFG is set only
when CLK falls.
*/
/* CLK is low. */
ASSERT_CLOCK_LOW();
/* Check that external triggers with sync async do not trigger when
* clock does not advance. */
ASSERT_NO_CAPTURE();
ASSERT_CCI_LOW();
HALF_TRIGGER();
ASSERT_NO_CAPTURE();
ASSERT_CCI_HIGH();
HALF_TRIGGER();
ASSERT_NO_CAPTURE();
ASSERT_CCI_LOW();
/* Advance the clock. No action on rising edge. */
last_outclk = outclk;
HALF_TICK_OUTCLK();
BSP430_UNITTEST_ASSERT_EQUAL_FMTx(outclk, last_outclk+1);
BSP430_UNITTEST_ASSERT_EQUAL_FMTx(outclk, timer_hpl->r);
ASSERT_NO_CAPTURE();
ASSERT_CCI_LOW();
ASSERT_CLOCK_HIGH();
/* Falling edge does not increment counter but does cause capture */
last_outclk = outclk;
HALF_TICK_OUTCLK();
BSP430_UNITTEST_ASSERT_EQUAL_FMTx(outclk, last_outclk);
BSP430_UNITTEST_ASSERT_EQUAL_FMTx(outclk, timer_hpl->r);
ASSERT_YES_CAPTURE();
ASSERT_CCI_LOW();
CLEAR_CAPTURE();
/*
F2) CCI rises then falls while CLK remains high. CCIFG remains low. When
CLK falls CCIFG is set.
*/
/* Advance the clock. No action on rising edge. */
last_outclk = outclk;
HALF_TICK_OUTCLK();
BSP430_UNITTEST_ASSERT_EQUAL_FMTx(outclk, last_outclk+1);
BSP430_UNITTEST_ASSERT_EQUAL_FMTx(outclk, timer_hpl->r);
ASSERT_NO_CAPTURE();
ASSERT_CCI_LOW();
ASSERT_CLOCK_HIGH();
/* Check that external triggers with sync async do not trigger when
* clock does not advance. */
ASSERT_NO_CAPTURE();
ASSERT_CCI_LOW();
HALF_TRIGGER();
ASSERT_NO_CAPTURE();
ASSERT_CCI_HIGH();
HALF_TRIGGER();
ASSERT_NO_CAPTURE();
ASSERT_CCI_LOW();
/* Falling edge does not increment counter but does cause capture */
last_outclk = outclk;
HALF_TICK_OUTCLK();
BSP430_UNITTEST_ASSERT_EQUAL_FMTx(outclk, last_outclk);
BSP430_UNITTEST_ASSERT_EQUAL_FMTx(outclk, timer_hpl->r);
ASSERT_YES_CAPTURE();
ASSERT_CCI_LOW();
CLEAR_CAPTURE();
/* Now test it with internal toggles. First, asynchronous: */
timer_hpl->cctl[APP_CCIDX] = CM_3 | CCIS_2 | SCCI | CAP;
ASSERT_NO_CAPTURE();
ASSERT_INTERNAL_TRIGGER_LOW();
ASSERT_CCI_LOW();
HALF_TRIGGER();
ASSERT_CCI_LOW();
ASSERT_NO_CAPTURE();
INTERNAL_HALF_TRIGGER();
ASSERT_CCI_HIGH();
ASSERT_INTERNAL_TRIGGER_HIGH();
ASSERT_YES_CAPTURE();
CLEAR_CAPTURE();
HALF_TRIGGER();
ASSERT_CCI_HIGH();
ASSERT_NO_CAPTURE();
INTERNAL_HALF_TRIGGER();
ASSERT_CCI_LOW();
ASSERT_INTERNAL_TRIGGER_LOW();
ASSERT_YES_CAPTURE();
ASSERT_CCI_LOW();
CLEAR_CAPTURE();
/* Now synchronous */
timer_hpl->cctl[APP_CCIDX] |= SCS;
ASSERT_NO_CAPTURE();
ASSERT_INTERNAL_TRIGGER_LOW();
INTERNAL_HALF_TRIGGER();
ASSERT_INTERNAL_TRIGGER_HIGH();
ASSERT_NO_CAPTURE();
INTERNAL_HALF_TRIGGER();
ASSERT_INTERNAL_TRIGGER_LOW();
ASSERT_NO_CAPTURE();
/* Advance the clock. No action on rising edge. */
last_outclk = outclk;
HALF_TICK_OUTCLK();
BSP430_UNITTEST_ASSERT_EQUAL_FMTx(outclk, last_outclk+1);
BSP430_UNITTEST_ASSERT_EQUAL_FMTx(outclk, timer_hpl->r);
ASSERT_NO_CAPTURE();
ASSERT_CCI_LOW();
ASSERT_CLOCK_HIGH();
/* Falling edge does not increment counter but does cause capture */
last_outclk = outclk;
HALF_TICK_OUTCLK();
BSP430_UNITTEST_ASSERT_EQUAL_FMTx(outclk, last_outclk);
BSP430_UNITTEST_ASSERT_EQUAL_FMTx(outclk, timer_hpl->r);
ASSERT_YES_CAPTURE();
ASSERT_CCI_LOW();
CLEAR_CAPTURE();
cprintf("%u: Timer: R %04x CTL %04x CCR %04x CCTL %04x\n", __LINE__, timer_hpl->r, timer_hpl->ctl, timer_hpl->ccr[APP_CCIDX], timer_hpl->cctl[APP_CCIDX]);
vBSP430unittestFinalize();
}
