//=============================================================================
// hal_SdioSleep
//-----------------------------------------------------------------------------
/// This function release the resource to #HAL_SYS_FREQ_32K.
//=============================================================================
PUBLIC VOID hal_SdioSleep(VOID)
{
// We just release the resource, because the clock gating in sdmmc controller
// will disable the clock. We should wait for the clock to be actually disabled
// but the module does not seam to have a status for that...
// Free a resource
// hwp_sysCtrl->Clk_Per_Disable |= SYS_CTRL_DISABLE_PER_SDMMC2;//modify 2012-02-24 ,wuys
//wifi_i2c_rf_write_data(0x3f, 0x0000,1);
//hwp_gpio->gpio_oen_set_out =
//hal_SdioGpioSet();
#if 0
hwp_configRegs->GPIO_Mode |= 0x1D000;;//modify 2012-02-24 ,wuys
//hwp_configRegs->Alt_mux_select |= 0x800;//modify 2012-02-24 ,wuys
hwp_configRegs->Alt_mux_select &= ~0x800;//modify 2012-02-24 ,wuys
#endif
hal_SysRequestFreq(HAL_SYS_FREQ_SDMMC2, HAL_SYS_FREQ_32K, NULL);
// hwp_sysCtrl->Clk_Per_Disable |= SYS_CTRL_DISABLE_PER_SDMMC2;//modify 2012-02-24 ,wuys
//hal_SdioSetClk(100000);
}
// =============================================================================
// hal_AifClose
// -----------------------------------------------------------------------------
/// Close the AIF.
// =============================================================================
PUBLIC VOID hal_AifClose(VOID)
{
hwp_aif->ctrl = 0;
hwp_aif->serial_ctrl = AIF_MASTER_MODE_MASTER;
hwp_aif->side_tone = 0;
#if (CHIP_ASIC_ID == CHIP_ASIC_ID_GALLITE)
hwp_sysCtrl->Cfg_Aif_Tx_Stb_Div = 0;
#endif // (CHIP_ASIC_ID == CHIP_ASIC_ID_GALLITE)
// Reset AIF module, to force output lines (I2S clocks and data lines)
// to be low.
hwp_sysCtrl->REG_DBG = SYS_CTRL_PROTECT_UNLOCK;
hwp_sysCtrl->BB_Rst_Set=SYS_CTRL_SET_RST_AIF;
hwp_sysCtrl->REG_DBG = SYS_CTRL_PROTECT_LOCK;
#if (CHIP_ASIC_ID == CHIP_ASIC_ID_GALLITE)
if (g_halAifFreqSrcAbbSetting & ABB_AIF_FREQ_SRC_DIV_BY_2)
{
g_halAifFreqSrcAbbSetting &= ~ABB_AIF_FREQ_SRC_DIV_BY_2;
hal_AbbRegWrite(CODEC_FUNC_FREQ_SAMPLE_SEL, g_halAifFreqSrcAbbSetting);
g_halAifFreqSrcAbbSetting = 0;
}
#endif // (CHIP_ASIC_ID == CHIP_ASIC_ID_GALLITE)
g_halAifOpened = FALSE;
g_halAifPlaying = FALSE;
g_halAifRecording = FALSE;
// Release the resource
hal_SysRequestFreq(HAL_SYS_FREQ_AIF, HAL_SYS_FREQ_32K, NULL);
}
//=============================================================================
// hal_SdioWakeUp
//-----------------------------------------------------------------------------
/// This function requests a resource of #HAL_SYS_FREQ_52M.
/// hal_SdioSleep() must be called before any other
//=============================================================================
PUBLIC VOID hal_SdioWakeUp(VOID)
{
// Take a resource (The idea is to be able to get a 25Mhz clock)
// hwp_sysCtrl->Clk_Per_Enable |= SYS_CTRL_ENABLE_PER_SDMMC2;//modify 2012-02-24 ,wuys
// wifi_i2c_rf_write_data(0x3f, 0x0000,1);
hal_SysRequestFreq(HAL_SYS_FREQ_SDMMC2, HAL_SYS_FREQ_104M, hal_SdioUpdateDivider);
UINT32 scStatus = hal_SysEnterCriticalSection();
// Make sure the last clock is set
hal_SdioUpdateDivider(hal_SysGetFreq());
hal_SysExitCriticalSection(scStatus);
// hwp_configRegs->GPIO_Mode &= ~CFG_REGS_MODE_PIN_SPI1_CLK;//modify 2012-02-24 ,wuys
#if 0
hwp_configRegs->GPIO_Mode &= ~0x1D000;;//modify 2012-02-24 ,wuys
// hwp_configRegs->Alt_mux_select &= ~0x800;//modify 2012-02-24 ,wuys
hwp_configRegs->Alt_mux_select |= 0x800;//modify 2012-02-24 ,wuys
#endif
//hal_SdioGpioClr();
//hwp_gpio->gpio_oen_set_out
//hwp_sysCtrl->Clk_Per_Enable |= SYS_CTRL_ENABLE_PER_SDMMC2;//modify 2012-02-24 ,wuys
//hal_SdioSetClk(2000000);
}
PUBLIC VOID hal_SdioOpen(UINT8 clk_adj, HAL_SDIO_IRQ_HANDLER_T handler)
{
g_halSdioRegistry = handler;
// Take the module out of reset
hwp_sysCtrl->REG_DBG = SYS_CTRL_PROTECT_UNLOCK;
hwp_sysCtrl->BB_Rst_Clr = SYS_CTRL_CLR_RST_SDMMC2;
hwp_sysCtrl->Clk_Per_Enable |= SYS_CTRL_ENABLE_PER_SDMMC2;
hwp_sysCtrl->Clk_Sys_Mode |= SYS_CTRL_MODE_SYS_PCLK_DATA_MANUAL;
// hwp_sysCtrl->Sys_Rst_Clr = SYS_CTRL_CLR_RST_SDMMC2;
hwp_sysCtrl->REG_DBG = SYS_CTRL_PROTECT_LOCK;
// We don't use interrupts.
// hwp_sdmmc2->SDMMC2_INT_MASK = 0x80;
hwp_sdmmc2->SDMMC2_INT_MASK = 0x00;
hwp_sdmmc2->SDMMC2_MCLK_ADJUST = clk_adj;
// Take a resource (The idea is to be able to get a 25Mhz clock)
hal_SysRequestFreq(HAL_SYS_FREQ_SDMMC2, HAL_SYS_FREQ_104M, hal_SdioUpdateDivider);
UINT32 scStatus = hal_SysEnterCriticalSection();
// Make sure the last clock is set
hal_SdioUpdateDivider(hal_SysGetFreq());
hal_SysExitCriticalSection(scStatus);
// pmd_EnablePower(PMD_POWER_SDMMC2, TRUE);
}
PROTECTED VOID hal_AifSleep(VOID)
{
if (hal_AifResourceMgmt() == TRUE)
{
HAL_ASSERT(FALSE, "AIF Sleep called when AIF still in use!");
}
// release the resource
hal_SysRequestFreq(HAL_SYS_FREQ_AIF, HAL_SYS_FREQ_32K, NULL);
}
// =============================================================================
// hal_PwmResourceMgmt
// -----------------------------------------------------------------------------
/// Checks if any components in the PWM module are active and requests or
/// releases the resource. The return value is TRUE if the resource is
/// active and FALSE otherwise.
// =============================================================================
PROTECTED BOOL hal_PwmResourceMgmt(VOID)
{
// If ANY PWL or PWT is active, request resource, otherwise
// release resource
if ((hwp_pwm->PWL0_Config & PWM_PWL0_EN_H) != 0)
{
hal_SysRequestFreq(HAL_SYS_FREQ_PWM, HAL_SYS_FREQ_26M, hal_PwmUpdateDivider);
return TRUE;
}
if ((hwp_pwm->PWL1_Config & PWM_PWL1_EN_H) != 0)
{
hal_SysRequestFreq(HAL_SYS_FREQ_PWM, HAL_SYS_FREQ_26M, hal_PwmUpdateDivider);
return TRUE;
}
if ((hwp_pwm->PWT_Config & PWM_PWT_ENABLE) != 0)
{
hal_SysRequestFreq(HAL_SYS_FREQ_PWM, HAL_SYS_FREQ_26M, hal_PwmUpdateDivider);
return TRUE;
}
hal_SysRequestFreq(HAL_SYS_FREQ_PWM, HAL_SYS_FREQ_32K, NULL);
return FALSE;
}
//=============================================================================
// hal_SdioClose
//-----------------------------------------------------------------------------
/// Close the SDMMC2 module. Take a resource.
//=============================================================================
PUBLIC VOID hal_SdioClose(VOID)
{
g_halSdioRegistry = NULL;
// pmd_EnablePower(PMD_POWER_SDMMC2, FALSE);
// Free a resource
hal_SysRequestFreq(HAL_SYS_FREQ_SDMMC2, HAL_SYS_FREQ_32K, NULL);
// Put the module in reset, as its clock is free running.
hwp_sysCtrl->REG_DBG = SYS_CTRL_PROTECT_UNLOCK;
hwp_sysCtrl->Clk_Per_Disable = SYS_CTRL_DISABLE_PER_SDMMC2;
hwp_sysCtrl->BB_Rst_Set = SYS_CTRL_SET_RST_SDMMC2;
hwp_sysCtrl->REG_DBG = SYS_CTRL_PROTECT_LOCK;
}
// =============================================================================
// hal_AifOpen
// -----------------------------------------------------------------------------
/// Open the AIF and set the appropriate config.
/// When the analog interface is used, leave the \c serialCfg field of the
/// \c config parameter at 0.
///
/// @param config Pointer to the configuration of the Audio InterFace.
/// @return HAL_ERR_NO if everything is alright or HAL_ERR_RESOURCE_BUSY if
/// the AIF has already been opened.
// =============================================================================
PUBLIC HAL_ERR_T hal_AifOpen(CONST HAL_AIF_CONFIG_T* config)
{
UINT32 controlReg = 0;
UINT32 serialCfgReg = 0;
UINT32 lrck;
UINT32 bck;
UINT32 clkDivider;
UINT32 bckLrckDivider;
// Pointer to the serial config
HAL_AIF_SERIAL_CFG_T* serialCfg;
// Already opened ?
if (g_halAifOpened == TRUE)
{
return HAL_ERR_RESOURCE_BUSY;
}
// set the resource as active
hal_SysRequestFreq(HAL_SYS_FREQ_AIF, HAL_SYS_FREQ_26M, NULL);
// Unrest AIF module.
hwp_sysCtrl->REG_DBG = SYS_CTRL_PROTECT_UNLOCK;
hwp_sysCtrl->BB_Rst_Clr = SYS_CTRL_CLR_BB_RST(SYS_CTRL_CLR_RST_AIF);
hwp_sysCtrl->REG_DBG = SYS_CTRL_PROTECT_UNLOCK;
#if (CHIP_ASIC_ID == CHIP_ASIC_ID_GALLITE)
#ifdef GALLITE_IS_CT1129
clkDivider = AIF_SOURCE_CLOCK / config->sampleRate - 2;
#else
if (config->sampleRate < HAL_AIF_FREQ_12000HZ)
{
hal_AbbRegBlockingRead(CODEC_FUNC_FREQ_SAMPLE_SEL, &g_halAifFreqSrcAbbSetting);
g_halAifFreqSrcAbbSetting |= ABB_AIF_FREQ_SRC_DIV_BY_2;
hal_AbbRegWrite(CODEC_FUNC_FREQ_SAMPLE_SEL, g_halAifFreqSrcAbbSetting);
clkDivider = AIF_SOURCE_CLOCK / 2 / config->sampleRate - 2;
}
else
{
clkDivider = AIF_SOURCE_CLOCK / config->sampleRate - 2;
}
#endif
hwp_sysCtrl->Cfg_Aif_Tx_Stb_Div = SYS_CTRL_AIF_TX_STB_EN
| SYS_CTRL_AIF_TX_STB_DIV(clkDivider);
#endif // (CHIP_ASIC_ID == CHIP_ASIC_ID_GALLITE)
if (config->interface == HAL_AIF_IF_PARALLEL)
{
// Analog mode
controlReg = AIF_PARALLEL_OUT_SET_PARA | AIF_PARALLEL_IN_SET_PARA | AIF_LOOP_BACK_NORMAL;
serialCfgReg = AIF_MASTER_MODE_MASTER; // Well, it's analog mode ...
}
else if (config->interface == HAL_AIF_IF_PARALLEL_STEREO)
{
#if (CHIP_HAS_STEREO_DAC == 1)
#if ((CHIP_ASIC_ID == CHIP_ASIC_ID_GALLITE) || (CHIP_ASIC_ID == CHIP_ASIC_ID_ESPERITE))
controlReg = AIF_PARALLEL_OUT_SET_PARA | AIF_PARALLEL_IN_SET_PARA | AIF_LOOP_BACK_NORMAL | AIF_TX_STB_MODE;
#else
controlReg = AIF_PARALLEL_OUT_SET_PARA | AIF_PARALLEL_IN_SET_PARA | AIF_LOOP_BACK_NORMAL | AIF_TX_PARALLEL_EXT;
#endif
if (config->channelNb == HAL_AIF_MONO)
{
serialCfgReg = AIF_MASTER_MODE_MASTER | AIF_TX_MODE_MONO_STEREO_DUPLI;
}
else
{
serialCfgReg = AIF_MASTER_MODE_MASTER | AIF_TX_MODE_STEREO_STEREO;
}
#else
HAL_ASSERT(FALSE, "This chip has not the Parallel Stereo Interface.");
#endif
}
else
{
// Digital (serial) modes
serialCfgReg = 0;
if (config->serialCfg == NULL)
{
HAL_ASSERT(FALSE, "hal_AifOpen in serial mode without serial config\n");
}
else
{
if (config->interface == HAL_AIF_IF_SERIAL ||
config->interface == HAL_AIF_IF_SERIAL_1 ||
config->interface == HAL_AIF_IF_SERIAL_2)
{
// Serial in and serial out
controlReg = AIF_PARALLEL_OUT_CLR_PARA |
AIF_PARALLEL_IN_CLR_PARA |
AIF_LOOP_BACK_NORMAL;
}
else
{
// Serial in and parallel out
#if (CHIP_ASIC_ID == CHIP_ASIC_ID_GALLITE)
controlReg = AIF_PARALLEL_OUT_SET_PARA |
AIF_PARALLEL_IN_CLR_PARA |
AIF_LOOP_BACK_NORMAL|
AIF_TX_STB_MODE;
#elif (CHIP_ASIC_ID == CHIP_ASIC_ID_GREENSTONE)
controlReg = AIF_PARALLEL_OUT_SET_PARA |
AIF_PARALLEL_IN_CLR_PARA |
AIF_LOOP_BACK_NORMAL|
AIF_TX_PARALLEL_EXT;
#endif
}
// Mode
serialCfg = config->serialCfg;
HAL_ASSERT((serialCfg->mode < HAL_SERIAL_MODE_QTY),
"Improper serial mode");
serialCfgReg |= AIF_SERIAL_MODE(serialCfg->mode);
// TODO FIXME Implement the clock configuration
// here from the sample rate given at the aif opening
// FIXME
#if (CHIP_HAS_I2S_DI_1 == 1)
if (config->interface == HAL_AIF_IF_SERIAL_2 ||
config->interface == HAL_AIF_IF_SERIAL_2_IN_PARALLEL_OUT)
{
serialCfgReg |= AIF_I2S_IN_SEL_I2S_IN_2;
}
else if (config->interface == HAL_AIF_IF_SERIAL_1 ||
config->interface == HAL_AIF_IF_SERIAL_1_IN_PARALLEL_OUT)
{
serialCfgReg |= AIF_I2S_IN_SEL_I2S_IN_1;
}
else // HAL_AIF_IF_SERIAL or HAL_AIF_IF_SERIAL_IN_PARALLEL_OUT
{
serialCfgReg |= AIF_I2S_IN_SEL_I2S_IN_0;
}
#else
HAL_ASSERT(config->interface == HAL_AIF_IF_SERIAL ||
config->interface == HAL_AIF_IF_SERIAL_IN_PARALLEL_OUT,
"There is only one serial interface available");
#endif
// Master
if (serialCfg->aifIsMaster)
{
serialCfgReg |= AIF_MASTER_MODE_MASTER;
}
else
{
serialCfgReg |= AIF_MASTER_MODE_SLAVE;
}
// LSB first
if (serialCfg->lsbFirst)
{
serialCfgReg |= AIF_LSB_LSB;
}
else
{
serialCfgReg |= AIF_LSB_MSB;
}
// LRCK polarity
if (serialCfg->polarity)
{
serialCfgReg |= AIF_LRCK_POL_LEFT_L_RIGHT_H;
}
else
{
serialCfgReg |= AIF_LRCK_POL_LEFT_H_RIGHT_L;
}
// Rx delay
HAL_ASSERT(serialCfg->rxDelay<HAL_AIF_RX_DELAY_QTY,
"Improper delay for serial Rx");
serialCfgReg |= AIF_RX_DLY(serialCfg->rxDelay);
// Tx delay
if (serialCfg->txDelay == HAL_AIF_TX_DELAY_ALIGN)
{
serialCfgReg |= AIF_TX_DLY_ALIGN;
}
else
{
serialCfgReg |= AIF_TX_DLY_DLY_1;
}
// Rx Mode
if (serialCfg->rxMode == HAL_AIF_RX_MODE_STEREO_STEREO)
{
serialCfgReg |= AIF_RX_MODE_STEREO_STEREO;
}
else
{
serialCfgReg |= AIF_RX_MODE_STEREO_MONO_FROM_L;
}
// Tx Mode
HAL_ASSERT(serialCfg->txMode < HAL_AIF_TX_MODE_QTY,
"Improper mode for serial Tx" );
serialCfgReg |= AIF_TX_MODE(serialCfg->txMode);
// LRCK frequency ...
lrck = serialCfg->fs;
bck = lrck * serialCfg->bckLrckRatio;
// We get the BCK from the the audio clock.
clkDivider = (FAST_CLOCK_156M / bck) - 2;
hwp_sysCtrl->Cfg_Clk_AudioBCK_Div = SYS_CTRL_AUDIOBCK_DIVIDER(clkDivider);
// The ratio is calculated differently depending
// on whether we're using voice or audio mode.
if (serialCfg->mode == HAL_SERIAL_MODE_VOICE)
{
// Check the ratio
HAL_ASSERT(serialCfg->bckLrckRatio >= VOICE_BCK_LRCK_RATIO_MIN
&& serialCfg->bckLrckRatio<=VOICE_BCK_LRCK_RATIO_MAX,
"HAL: AIF: In voice mode, ratio is from %d to %d, %d unsupported",
VOICE_BCK_LRCK_RATIO_MIN,
VOICE_BCK_LRCK_RATIO_MAX,
serialCfg->bckLrckRatio);
bckLrckDivider = serialCfg->bckLrckRatio - 16;
}
else
{
HAL_ASSERT(serialCfg->bckLrckRatio >= AUDIO_BCK_LRCK_RATIO_MIN
&& serialCfg->bckLrckRatio<=AUDIO_BCK_LRCK_RATIO_MAX,
"HAL: AIF: In audio mode, ratio is from %d to %d, %d unsupported",
AUDIO_BCK_LRCK_RATIO_MIN,
AUDIO_BCK_LRCK_RATIO_MAX,
serialCfg->bckLrckRatio);
bckLrckDivider = serialCfg->bckLrckRatio/2 - 16;
}
serialCfgReg |= AIF_BCK_LRCK(bckLrckDivider);
// BCK polarity
if (serialCfg->invertBck)
{
serialCfgReg |= AIF_BCK_POL_INVERT;
}
else
{
serialCfgReg |= AIF_BCK_POL_NORMAL;
}
// Output Half Cycle Delay
if (serialCfg->outputHalfCycleDelay)
{
serialCfgReg |= AIF_OUTPUT_HALF_CYCLE_DLY_DLY;
}
else
{
serialCfgReg |= AIF_OUTPUT_HALF_CYCLE_DLY_NO_DLY;
}
// Input Half Cycle Delay
if (serialCfg->inputHalfCycleDelay)
{
serialCfgReg |= AIF_INPUT_HALF_CYCLE_DLY_DLY;
}
else
{
serialCfgReg |= AIF_INPUT_HALF_CYCLE_DLY_NO_DLY;
}
// BckOut gating
if (serialCfg->enableBckOutGating)
{
serialCfgReg |= AIF_BCKOUT_GATE_GATED;
}
else
{
serialCfgReg |= AIF_BCKOUT_GATE_NO_GATE;
}
}
}
// Initializes global variables
g_halAifHandlers[RECORD].halfHandler = NULL;
g_halAifHandlers[RECORD].endHandler = NULL;
g_halAifHandlers[PLAY].halfHandler = NULL;
g_halAifHandlers[PLAY].endHandler = NULL;
g_halAifPlaying = FALSE;
g_halAifRecording = FALSE;
// Write register
hwp_aif->serial_ctrl = serialCfgReg;
// hwp_aif->ctrl = controlReg;
g_halAifControlReg = controlReg;
#ifdef FPGA
#if (CHIP_HAS_ACCO_AUDIO)
// Manual setting of the pll clock
hwp_sysCtrl->REG_DBG = SYS_CTRL_PROTECT_UNLOCK;
hwp_anaAccoFe->pll_ctrl = ANA_ACCO_PLL_PD_N_ENABLE;
hwp_sysCtrl->REG_DBG = SYS_CTRL_PROTECT_LOCK;
#endif
#endif
return HAL_ERR_NO;
}
PROTECTED VOID hal_AifWakeup(VOID)
{
// set the resource as active
hal_SysRequestFreq(HAL_SYS_FREQ_AIF, HAL_SYS_FREQ_26M, NULL);
}
