void hal_nrf_close_pipe(hal_nrf_address_t pipe_num)
{
en_pipes_t en_rxaddr;
en_pipes_t en_aa;
en_rxaddr.value = hal_nrf_read_reg (EN_RXADDR);
en_aa.value = hal_nrf_read_reg (EN_AA);
switch(pipe_num)
{
case HAL_NRF_PIPE0:
case HAL_NRF_PIPE1:
case HAL_NRF_PIPE2:
case HAL_NRF_PIPE3:
case HAL_NRF_PIPE4:
case HAL_NRF_PIPE5:
en_rxaddr.value = en_rxaddr.value & (uint8_t)~SET_BIT(pipe_num);
en_aa.value = en_aa.value & (uint8_t)~SET_BIT(pipe_num);
break;
case HAL_NRF_ALL:
en_rxaddr.value = 0U;
en_aa.value = 0U;
break;
case HAL_NRF_TX:
default:
break;
}
hal_nrf_write_reg (EN_RXADDR, en_rxaddr.value);
hal_nrf_write_reg (EN_AA, en_aa.value);
}
void hal_nrf_open_pipe(hal_nrf_address_t pipe_num, bool auto_ack)
{
en_pipes_t en_rxaddr;
en_pipes_t en_aa;
en_rxaddr.value = hal_nrf_read_reg (EN_RXADDR);
en_aa.value = hal_nrf_read_reg (EN_AA);
switch(pipe_num)
{
case HAL_NRF_PIPE0:
case HAL_NRF_PIPE1:
case HAL_NRF_PIPE2:
case HAL_NRF_PIPE3:
case HAL_NRF_PIPE4:
case HAL_NRF_PIPE5:
en_rxaddr.value = en_rxaddr.value | SET_BIT(pipe_num);
if(auto_ack)
{
en_aa.value = en_aa.value | SET_BIT(pipe_num);
}
else
{
en_aa.value = en_aa.value & (uint8_t)~SET_BIT(pipe_num);
}
break;
case HAL_NRF_ALL:
en_rxaddr.value = (uint8_t)(~(BIT_6|BIT_7));
if(auto_ack)
{
en_aa.value = (uint8_t)(~(BIT_6|BIT_7));
}
else
{
en_aa.value = 0U;
}
break;
case HAL_NRF_TX:
default:
break;
}
hal_nrf_write_reg (EN_RXADDR, en_rxaddr.value);
hal_nrf_write_reg (EN_AA, en_aa.value);
}
void hal_nrf_enable_dynamic_payload(bool enable)
{
feature_t feature;
feature.value = hal_nrf_read_reg (FEATURE);
feature.bits.en_dpl = (enable) ? 1 : 0;
hal_nrf_write_reg (FEATURE, feature.value);
}
void hal_nrf_enable_ack_payload(bool enable)
{
feature_t feature;
feature.value = hal_nrf_read_reg (FEATURE);
feature.bits.en_ack_pay = (enable) ? 1U : 0U;
hal_nrf_write_reg (FEATURE, feature.value);
}
void hal_nrf_enable_dynamic_ack(bool enable)
{
feature_t feature;
feature.value = hal_nrf_read_reg (FEATURE);
feature.bits.en_dyn_ack = (enable) ? 1U : 0U;
hal_nrf_write_reg (FEATURE, feature.value);
}
void hal_nrf_set_pll_mode(bool pll_lock)
{
rf_setup_t rf_setup;
rf_setup.value = hal_nrf_read_reg (RF_SETUP);
rf_setup.bits.pll_lock = (pll_lock) ? 1U : 0U;
hal_nrf_write_reg(RF_SETUP, rf_setup.value);
}
void hal_nrf_enable_continious_wave (bool enable)
{
rf_setup_t rf_setup;
rf_setup.value = hal_nrf_read_reg (RF_SETUP);
rf_setup.bits.cont_wave = (enable ? 1U : 0U);
hal_nrf_write_reg(RF_SETUP, rf_setup.value);
}
void hal_nrf_set_output_power(hal_nrf_output_power_t power)
{
rf_setup_t rf_setup;
rf_setup.value = hal_nrf_read_reg (RF_SETUP);
rf_setup.bits.rf_pwr = (uint8_t)power;
hal_nrf_write_reg (RF_SETUP, rf_setup.value);
}
uint8_t hal_nrf_clear_irq_flags_get_status(void)
{
uint8_t retval;
// When RFIRQ is cleared (when calling write_reg), pipe information is unreliable (read again with read_reg)
retval = hal_nrf_write_reg (STATUS, (BIT_6|BIT_5|BIT_4)) & (BIT_6|BIT_5|BIT_4);
retval |= hal_nrf_read_reg (STATUS) & (BIT_3|BIT_2|BIT_1|BIT_0);
return (retval);
}
hal_nrf_operation_mode_t hal_nrf_get_operation_mode()
{
config_t config;
config.value = hal_nrf_read_reg (CONFIG);
if(config.bits.prim_rx == 1)
return HAL_NRF_PRX;
else
return HAL_NRF_PTX;
}
uint8_t hal_nrf_get_pipe_status(uint8_t pipe_num)
{
en_pipes_t en_rxaddr;
en_pipes_t en_aa;
uint8_t en_rx_r, en_aa_r;
en_rxaddr.value = hal_nrf_read_reg (EN_RXADDR);
en_aa.value = hal_nrf_read_reg (EN_AA);
switch (pipe_num)
{
case 0:
en_rx_r = en_rxaddr.bits.pipe_0;
en_aa_r = en_aa.bits.pipe_0;
break;
case 1:
en_rx_r = en_rxaddr.bits.pipe_1;
en_aa_r = en_aa.bits.pipe_1;
break;
case 2:
en_rx_r = en_rxaddr.bits.pipe_2;
en_aa_r = en_aa.bits.pipe_2;
break;
case 3:
en_rx_r = en_rxaddr.bits.pipe_3;
en_aa_r = en_aa.bits.pipe_3;
break;
case 4:
en_rx_r = en_rxaddr.bits.pipe_4;
en_aa_r = en_aa.bits.pipe_4;
break;
case 5:
en_rx_r = en_rxaddr.bits.pipe_5;
en_aa_r = en_aa.bits.pipe_5;
break;
default:
en_rx_r = 0U;
en_aa_r = 0U;
break;
}
return (uint8_t)(en_aa_r << 1) + en_rx_r;
}
uint8_t hal_nrf_get_rx_payload_width(uint8_t pipe_num)
{
uint8_t pw;
switch (pipe_num)
{
case 0:
pw = hal_nrf_read_reg (RX_PW_P0);
break;
case 1:
pw = hal_nrf_read_reg (RX_PW_P1);
break;
case 2:
pw = hal_nrf_read_reg (RX_PW_P2);
break;
case 3:
pw = hal_nrf_read_reg (RX_PW_P3);
break;
case 4:
pw = hal_nrf_read_reg (RX_PW_P4);
break;
case 5:
pw = hal_nrf_read_reg (RX_PW_P5);
break;
default:
pw = 0U;
break;
}
return pw;
}
uint8_t hal_nrf_get_address(uint8_t address, uint8_t *addr)
{
switch (address)
{
case HAL_NRF_PIPE0:
case HAL_NRF_PIPE1:
case HAL_NRF_TX:
return (uint8_t)hal_nrf_read_multibyte_reg (address, addr);
default:
*addr = hal_nrf_read_reg(RX_ADDR_P0 + address);
return 1U;
}
}
void hal_nrf_set_operation_mode(hal_nrf_operation_mode_t op_mode)
{
config_t config;
config.value = hal_nrf_read_reg (CONFIG);
if(op_mode == HAL_NRF_PRX)
{
config.bits.prim_rx = 1U;
}
else
{
config.bits.prim_rx = 0U;
}
hal_nrf_write_reg (CONFIG, config.value);
}
void hal_nrf_set_power_mode(hal_nrf_pwr_mode_t pwr_mode)
{
config_t config;
config.value = hal_nrf_read_reg (CONFIG);
if(pwr_mode == HAL_NRF_PWR_UP)
{
config.bits.pwr_up = 1U;
}
else
{
config.bits.pwr_up = 0U;
}
hal_nrf_write_reg (CONFIG, config.value);
}
void hal_nrf_set_irq_mode(hal_nrf_irq_source_t int_source, bool irq_state)
{
config_t config;
config.value = hal_nrf_read_reg (CONFIG);
switch (int_source)
{
case HAL_NRF_MAX_RT:
config.bits.mask_max_rt = irq_state ? 0U : 1U;
break;
case HAL_NRF_TX_DS:
config.bits.mask_tx_ds = irq_state ? 0U : 1U;
break;
case HAL_NRF_RX_DR:
config.bits.mask_rx_dr = irq_state ? 0U : 1U;
break;
}
hal_nrf_write_reg (CONFIG, config.value);
}
void hal_nrf_set_crc_mode(hal_nrf_crc_mode_t crc_mode)
{
config_t config;
config.value = hal_nrf_read_reg (CONFIG);
switch (crc_mode)
{
case HAL_NRF_CRC_OFF:
config.bits.en_crc = 0U;
break;
case HAL_NRF_CRC_8BIT:
config.bits.en_crc = 1U;
config.bits.crc0 = 0U;
break;
case HAL_NRF_CRC_16BIT:
config.bits.en_crc = 1U;
config.bits.crc0 = 1U;
break;
default:
break;
}
hal_nrf_write_reg (CONFIG, config.value);
}
void hal_nrf_set_datarate(hal_nrf_datarate_t datarate)
{
rf_setup_t rf_setup;
rf_setup.value = hal_nrf_read_reg (RF_SETUP);
switch (datarate)
{
case HAL_NRF_250KBPS:
rf_setup.bits.rf_dr_low = 1U;
rf_setup.bits.rf_dr_high = 0U;
break;
case HAL_NRF_1MBPS:
rf_setup.bits.rf_dr_low = 0U;
rf_setup.bits.rf_dr_high = 0U;
break;
case HAL_NRF_2MBPS:
default:
rf_setup.bits.rf_dr_low = 0U;
rf_setup.bits.rf_dr_high = 1U;
break;
}
hal_nrf_write_reg (RF_SETUP, rf_setup.value);
}
uint8_t hal_nrf_get_packet_lost_ctr(void)
{
return ((hal_nrf_read_reg(OBSERVE_TX) & (BIT_7|BIT_6|BIT_5|BIT_4)) >> 4);
}
uint8_t hal_nrf_read_rx_payload_width(void)
{
return hal_nrf_read_reg(R_RX_PL_WID);
}
bool hal_nrf_get_carrier_detect(void)
{
return (bool)(hal_nrf_read_reg(CD) & 0x01U);
}
uint8_t hal_nrf_get_transmit_attempts(void)
{
return (hal_nrf_read_reg(OBSERVE_TX) & (BIT_3|BIT_2|BIT_1|BIT_0));
}
uint8_t hal_nrf_get_fifo_status(void)
{
return hal_nrf_read_reg(FIFO_STATUS);
}
uint8_t hal_nrf_get_rx_fifo_status(void)
{
return (hal_nrf_read_reg(FIFO_STATUS) & ((1U<<RX_FULL)|(1U<<RX_EMPTY)));
}
uint8_t hal_nrf_get_tx_fifo_status(void)
{
return ((hal_nrf_read_reg(FIFO_STATUS) & ((1U<<TX_FIFO_FULL)|(1U<<TX_EMPTY))) >> 4);
}
void main(void) {
int i = 0; // local counter
int total_pkt_count = 1;
int addr_width = 5;
int customized_plen = 0;
int pipe_num = 6;
epl_rf_en_auto_ack_t auto_ack = 0;
//int mode = 1; // 1 for sender mode, 2 for dumper mode
// new params
unsigned char pipe_source; // used to store pipe_source number
unsigned char ACKbuf[] = "ACK";
unsigned char temp_buf[34]; // used for dumper to get RF packets from RX FIFO
unsigned char temp_addr[5];
unsigned char data_length = 0;
unsigned char dynpd_pipe;
unsigned char addr_buf[5];
// set pin direction
P0EXP = 0x00;
P0ALT = 0x00;
P0DIR = 0x00;
// uart init
epl_uart_init(UART_BAUD_57K6);
//init usb connection
usb_init(); // Initialize USB
EA = 1; // Enable global IRQ
//Start RF tx mode
epl_rf_en_quick_init(cfg);
//Clear TX FIFO
hal_nrf_write_reg(FLUSH_TX, 0);
hal_nrf_write_reg(FLUSH_RX, 0);
hal_nrf_lock_unlock();
hal_nrf_enable_dynamic_pl();
LED_Blink(20);
epl_uart_putstr("start!");
while (1) {
usb_recv_packet();
switch (ubuf[1]) {
case EPL_SENDER_MODE:
customized_plen = 0;
for (i = 0; i < PLOAD_LEN; i++)
packet[i] = i + 9;
hal_nrf_close_pipe(HAL_NRF_PIPE1);
hal_nrf_close_pipe(HAL_NRF_PIPE2);
hal_nrf_close_pipe(HAL_NRF_PIPE3);
hal_nrf_close_pipe(HAL_NRF_PIPE4);
hal_nrf_close_pipe(HAL_NRF_PIPE5);
break;
case EPL_DUMPER_MODE:
hal_nrf_close_pipe(HAL_NRF_PIPE1);
hal_nrf_close_pipe(HAL_NRF_PIPE2);
hal_nrf_close_pipe(HAL_NRF_PIPE3);
hal_nrf_close_pipe(HAL_NRF_PIPE4);
hal_nrf_close_pipe(HAL_NRF_PIPE5);
break;
case EPL_OUTPUT_POWER: //Host:set_output_power
hal_nrf_set_output_power(ubuf[2]);
epl_uart_putstr("EPL_OUTPUT_POWER\n");
usb_send_packet(ACKbuf, 3);
epl_uart_putstr("EPL_OUTPUT_POWER END\n");
break;
case EPL_CHANNEL:
hal_nrf_set_rf_channel(ubuf[2]);
usb_send_packet(ACKbuf, 3);
break;
case EPL_DATARATE:
hal_nrf_set_datarate(ubuf[2]);
usb_send_packet(ACKbuf, 3);
break;
case EPL_ADDR_WIDTH:
addr_width = (int) ubuf[2];
hal_nrf_set_address_width(ubuf[2]);
usb_send_packet(ACKbuf, 3);
break;
case EPL_AUTOACK_P0:
auto_ack = ubuf[2];
usb_send_packet(ACKbuf, 3);
break;
case EPL_AUTOACK_P1:
auto_ack = ubuf[2];
usb_send_packet(ACKbuf, 3);
break;
case EPL_AUTOACK_P2:
auto_ack = ubuf[2];
usb_send_packet(ACKbuf, 3);
break;
case EPL_AUTOACK_P3:
auto_ack = ubuf[2];
usb_send_packet(ACKbuf, 3);
break;
case EPL_AUTOACK_P4:
auto_ack = ubuf[2];
usb_send_packet(ACKbuf, 3);
break;
case EPL_AUTOACK_P5:
auto_ack = ubuf[2];
usb_send_packet(ACKbuf, 3);
break;
case EPL_DATA_LENGTH_P0:
data_length = (int) ubuf[2];
epl_rf_en_rcv_pipe_config(HAL_NRF_PIPE0, temp_addr, data_length, auto_ack);
usb_send_packet(ACKbuf, 3);
break;
case EPL_DATA_LENGTH_P1:
data_length = (int) ubuf[2];
epl_rf_en_rcv_pipe_config(HAL_NRF_PIPE1, temp_addr, data_length, auto_ack);
usb_send_packet(ACKbuf, 3);
break;
case EPL_DATA_LENGTH_P2:
data_length = (int) ubuf[2];
epl_rf_en_rcv_pipe_config(HAL_NRF_PIPE2, temp_addr, data_length, auto_ack);
usb_send_packet(ACKbuf, 3);
break;
case EPL_DATA_LENGTH_P3:
data_length = (int) ubuf[2];
epl_rf_en_rcv_pipe_config(HAL_NRF_PIPE3, temp_addr, data_length, auto_ack);
usb_send_packet(ACKbuf, 3);
break;
case EPL_DATA_LENGTH_P4:
data_length = (int) ubuf[2];
epl_rf_en_rcv_pipe_config(HAL_NRF_PIPE4, temp_addr, data_length, auto_ack);
usb_send_packet(ACKbuf, 3);
break;
case EPL_DATA_LENGTH_P5:
data_length = (int) ubuf[2];
epl_rf_en_rcv_pipe_config(HAL_NRF_PIPE5, temp_addr, data_length, auto_ack);
usb_send_packet(ACKbuf, 3);
break;
case EPL_CRC_MODE:
if (ubuf[2] == 0)
hal_nrf_set_crc_mode(HAL_NRF_CRC_OFF);
else if (ubuf[2] == 2)
hal_nrf_set_crc_mode(HAL_NRF_CRC_8BIT);
else if (ubuf[2] == 3)
hal_nrf_set_crc_mode(HAL_NRF_CRC_16BIT);
else
;
usb_send_packet(ACKbuf, 3);
break;
case EPL_RX_ADDR_P0:
for (i = 0; i < addr_width; i++) {
temp_addr[i] = ubuf[i + 2];
}
hal_nrf_set_address(HAL_NRF_PIPE0, temp_addr);
epl_rf_en_set_dst_addr(temp_addr);
usb_send_packet(ACKbuf, 3);
break;
case EPL_RX_ADDR_P1:
for (i = 0; i < addr_width; i++) {
temp_addr[i] = ubuf[i + 2];
}
usb_send_packet(ACKbuf, 3);
break;
case EPL_RX_ADDR_P2:
for (i = 0; i < addr_width; i++) {
temp_addr[i] = ubuf[i + 2];
}
usb_send_packet(ACKbuf, 3);
break;
case EPL_RX_ADDR_P3:
for (i = 0; i < addr_width; i++) {
temp_addr[i] = ubuf[i + 2];
}
usb_send_packet(ACKbuf, 3);
break;
case EPL_RX_ADDR_P4:
for (i = 0; i < addr_width; i++) {
temp_addr[i] = ubuf[i + 2];
}
usb_send_packet(ACKbuf, 3);
break;
case EPL_RX_ADDR_P5:
for (i = 0; i < addr_width; i++) {
temp_addr[i] = ubuf[i + 2];
}
usb_send_packet(ACKbuf, 3);
break;
case EPL_USER_PLOAD:
if (ubuf[2] == USRS_PLOAD) {
customized_plen = (int) ubuf[3];
for (i = 0; i < customized_plen; i++) {
packet[i] = ubuf[i + 4];
}
} else {
customized_plen = 0;
for (i = 0; i < PLOAD_LEN; i++) {
packet[i] = i + 9;
}
}
usb_send_packet(ACKbuf, 3);
break;
case EPL_NEW_COUNTER:
total_pkt_count = 1;
usb_send_packet(ACKbuf, 3);
break;
/*20110221 celine*/
case EPL_DYNAMIC_PD:
dynpd_pipe = (int)ubuf[2];
if ((int)ubuf[3] == 01){
//hal_nrf_setup_dyn_pl(dynpd_pipe);
hal_nrf_write_reg(DYNPD, (1<<dynpd_pipe) | hal_nrf_read_reg(DYNPD));
} else {
//hal_nrf_lock_unlock();
//hal_nrf_enable_dynamic_pl();
hal_nrf_write_reg(DYNPD, ~(1<<dynpd_pipe) & hal_nrf_read_reg(DYNPD));
}
usb_send_packet(ACKbuf, 3);
break;
/**/
case EPL_RUN_SENDER:
epl_rf_en_enter_tx_mode();
// clear Tx irq
hal_nrf_clear_irq_flag(HAL_NRF_TX_DS);
hal_nrf_clear_irq_flag(HAL_NRF_MAX_RT);
if (ubuf[2] == AUTO_PLOAD) {
epl_uart_putstr("\nauto pload\r\n");
packet[0] = total_pkt_count++;
epl_rf_en_send(packet, data_length);
} else {
epl_uart_putstr("\nusrs pload\r\n");
epl_rf_en_send(packet, customized_plen);
}
LED_Blink(10);
array_cp(temp_buf, ACKbuf, 3);
temp_buf[3] = hal_nrf_read_reg(OBSERVE_TX) & 0x0F;
usb_send_packet(temp_buf, 4);
epl_rf_en_enter_rx_mode();
break;
case EPL_RUN_DUMPER:
hal_nrf_clear_irq_flag(HAL_NRF_RX_DR);
hal_nrf_flush_rx();
epl_rf_en_enter_rx_mode();
while (1) {
if (ubuf[1] == 0xf5) { // Host wants to terminate
epl_uart_putstr("Terminate !\r\n");
break;
}else if (hal_nrf_rx_fifo_empty() == 0) { // Rx_fifo is not empty
LED0_Toggle();
pipe_source = hal_nrf_get_rx_data_source();
hal_nrf_read_rx_pload(temp_buf);
// pending the data source on last byte
temp_buf[32] = pipe_source;
if(hal_nrf_read_reg(DYNPD)>>(int)pipe_source)
temp_buf[33] = hal_nrf_read_reg(RD_RX_PLOAD_W);
else
temp_buf[33] = hal_nrf_read_reg(RX_PW_P0+pipe_source);
// epl_uart_putstr("temp_buf[33] = ");
// epl_uart_puthex(temp_buf[33]);
// epl_uart_putstr("\r\n");
usb_send_packet(temp_buf, 34);
if((hal_nrf_read_reg(STATUS))&0x10){
hal_nrf_write_reg(FLUSH_TX, 0);
}
LED0_Toggle();
}
}
break;
case EPL_SHOW_CONFIG:
epl_uart_putstr("\r\n0. CONFIG = ");
epl_uart_puthex(hal_nrf_read_reg(CONFIG));
epl_uart_putstr("\r\n1. RF_CH = ");
epl_uart_puthex(hal_nrf_read_reg(RF_CH));
epl_uart_putstr("\r\n2. EN_AA = ");
epl_uart_puthex(hal_nrf_read_reg(EN_AA));
epl_uart_putstr("\r\n3. EN_RXADDR = ");
epl_uart_puthex(hal_nrf_read_reg(EN_RXADDR));
epl_uart_putstr("\r\n4. TX_ADDR = ");
hal_nrf_read_multibyte_reg(HAL_NRF_TX, addr_buf);
epl_uart_puthex(addr_buf[0]);
epl_uart_puthex(addr_buf[1]);
epl_uart_puthex(addr_buf[2]);
epl_uart_puthex(addr_buf[3]);
epl_uart_puthex(addr_buf[4]);
epl_uart_putstr("\r\n4. RX_ADDR_PO = ");
hal_nrf_read_multibyte_reg(HAL_NRF_PIPE0, addr_buf);
epl_uart_puthex(addr_buf[0]);
epl_uart_puthex(addr_buf[1]);
epl_uart_puthex(addr_buf[2]);
epl_uart_puthex(addr_buf[3]);
epl_uart_puthex(addr_buf[4]);
epl_uart_putstr("\r\n RX_ADDR_P1 = ");
hal_nrf_read_multibyte_reg(HAL_NRF_PIPE1, addr_buf);
epl_uart_puthex(addr_buf[0]);
epl_uart_puthex(addr_buf[1]);
epl_uart_puthex(addr_buf[2]);
epl_uart_puthex(addr_buf[3]);
epl_uart_puthex(addr_buf[4]);
epl_uart_putstr("\r\n RX_ADDR_P2 = ");
epl_uart_puthex(hal_nrf_read_reg(RX_ADDR_P2));
epl_uart_putstr("\r\n RX_ADDR_P3 = ");
epl_uart_puthex(hal_nrf_read_reg(RX_ADDR_P3));
epl_uart_putstr("\r\n RX_ADDR_P4 = ");
epl_uart_puthex(hal_nrf_read_reg(RX_ADDR_P4));
epl_uart_putstr("\r\n RX_ADDR_P5 = ");
epl_uart_puthex(hal_nrf_read_reg(RX_ADDR_P5));
epl_uart_putstr("\r\n5. RX_PW_P0 = ");
epl_uart_puthex(hal_nrf_read_reg(RX_PW_P0));
epl_uart_putstr("\r\n RX_PW_P1 = ");
epl_uart_puthex(hal_nrf_read_reg(RX_PW_P1));
epl_uart_putstr("\r\n RX_PW_P2 = ");
epl_uart_puthex(hal_nrf_read_reg(RX_PW_P2));
epl_uart_putstr("\r\n RX_PW_P3 = ");
epl_uart_puthex(hal_nrf_read_reg(RX_PW_P3));
epl_uart_putstr("\r\n RX_PW_P4 = ");
epl_uart_puthex(hal_nrf_read_reg(RX_PW_P4));
epl_uart_putstr("\r\n RX_PW_P5 = ");
epl_uart_puthex(hal_nrf_read_reg(RX_PW_P5));
epl_uart_putstr("\r\n6. RF_SETUP = ");
epl_uart_puthex(hal_nrf_read_reg(RF_SETUP));
epl_uart_putstr("\r\n7. STATUS = ");
epl_uart_puthex(hal_nrf_read_reg(STATUS));
epl_uart_putstr("\r\n8 .DYNPD = ");
epl_uart_puthex(hal_nrf_read_reg(DYNPD));
epl_uart_putstr("\r\n9. FEATURE = ");
epl_uart_puthex(hal_nrf_read_reg(FEATURE));
default:
break;
}// end switch case
uint8_t hal_nrf_get_auto_retr_status(void)
{
return hal_nrf_read_reg(OBSERVE_TX);
}
uint8_t hal_nrf_get_address_width (void)
{
return hal_nrf_read_reg (SETUP_AW) + 2U;
}
void radio_pl_init (const uint8_t *address, hal_nrf_operation_mode_t operational_mode)
{
hal_nrf_close_pipe(HAL_NRF_ALL); // First close all radio pipes
// Pipe 0 and 1 open by default
hal_nrf_open_pipe(HAL_NRF_PIPE0, true); // Then open pipe0, w/autoack
hal_nrf_set_crc_mode(HAL_NRF_CRC_16BIT); // Operates in 16bits CRC mode
hal_nrf_set_auto_retr(RF_RETRANSMITS, RF_RETRANS_DELAY);
// Enables auto retransmit.
// 3 retrans with 250ms delay
hal_nrf_set_address_width(HAL_NRF_AW_5BYTES); // 5 bytes address width
hal_nrf_set_address(HAL_NRF_TX, address); // Set device's addresses
hal_nrf_set_address(HAL_NRF_PIPE0, address); // Sets recieving address on
// pipe0
/*****************************************************************************
* Changed from esb/radio_esb.c *
* Enables: *
* - ACK payload *
* - Dynamic payload width *
* - Dynamic ACK *
*****************************************************************************/
hal_nrf_enable_ack_pl(); // Try to enable ack payload
// When the features are locked, the FEATURE and DYNPD are read out 0x00
// even after we have tried to enable ack payload. This mean that we need to
// activate the features.
if(hal_nrf_read_reg(FEATURE) == 0x00 && (hal_nrf_read_reg(DYNPD) == 0x00))
{
hal_nrf_lock_unlock (); // Activate features
hal_nrf_enable_ack_pl(); // Enables payload in ack
}
hal_nrf_enable_dynamic_pl(); // Enables dynamic payload
hal_nrf_setup_dyn_pl(ALL_PIPES); // Sets up dynamic payload on
// all data pipes.
/*****************************************************************************
* End changes from esb/radio_esb.c *
*****************************************************************************/
if(operational_mode == HAL_NRF_PTX) // Mode depentant settings
{
hal_nrf_set_operation_mode(HAL_NRF_PTX); // Enter TX mode
}
else
{
hal_nrf_set_operation_mode(HAL_NRF_PRX); // Enter RX mode
hal_nrf_set_rx_pload_width((uint8_t)HAL_NRF_PIPE0, RF_PAYLOAD_LENGTH);
// Pipe0 expect
// PAYLOAD_LENGTH byte payload
// PAYLOAD_LENGTH in radio.h
}
hal_nrf_set_rf_channel(RF_CHANNEL); // Operating on static channel
// Defined in radio.h.
// Frequenzy =
// 2400 + RF_CHANNEL
hal_nrf_set_power_mode(HAL_NRF_PWR_UP); // Power up device
start_timer(RF_POWER_UP_DELAY); // Wait for the radio to
wait_for_timer(); // power up
radio_set_status (RF_IDLE); // Radio now ready
}
bool hal_nrf_get_carrier_detect(void)
{
return hal_nrf_read_reg(CD) & 1;
}
