static void rtl8139_handle_interrupt(void)
{
ushort_t status;
volatile ushort_t* isr;
rtl8139_dev_t* dev;
dev = (rtl8139_dev_t*)g_device->priv;
/* interrupt status register */
isr = (ushort_t*)(dev->regs + RTL8139_REG_ISR);
status = *isr;
if (status & ((1 << 2) | (1 << 3)))
{
*isr = status;
rtl8139_disable_ints(dev->regs);
handle_tx_interrupt(dev->regs);
rtl8139_enable_ints(dev->regs);
}
else if (status & ((1 << 0) | (1 << 1) | (1 << 4)))
{
*isr = status;
rtl8139_disable_ints(dev->regs);
handle_rx_interrupt(dev->regs, status);
rtl8139_enable_ints(dev->regs);
}
else
NOT_IMPLEMENTED();
}
static void handle_spi_interrupt(const qm_spi_t spi)
{
qm_spi_reg_t *const controller = QM_SPI[spi];
const qm_spi_async_transfer_t *transfer = spi_async_transfer[spi];
const uint32_t int_status = controller->isr;
QM_ASSERT((int_status & (QM_SPI_ISR_TXOIS | QM_SPI_ISR_RXUIS)) == 0);
if (int_status & QM_SPI_ISR_RXOIS) {
if (transfer->callback) {
transfer->callback(transfer->callback_data, -EIO,
QM_SPI_RX_OVERFLOW, rx_counter[spi]);
}
controller->rxoicr;
controller->imr = QM_SPI_IMR_MASK_ALL;
controller->ssienr = 0;
return;
}
if (int_status & QM_SPI_ISR_RXFIS) {
handle_rx_interrupt(spi);
}
if (transfer->rx_len == rx_counter[spi] &&
transfer->tx_len == tx_counter[spi] &&
(controller->sr & QM_SPI_SR_TFE) &&
!(controller->sr & QM_SPI_SR_BUSY)) {
controller->imr = QM_SPI_IMR_MASK_ALL;
controller->ssienr = 0;
if (transfer->callback && tmode[spi] != QM_SPI_TMOD_RX) {
transfer->callback(transfer->callback_data, 0,
QM_SPI_IDLE, transfer->tx_len);
}
return;
}
if (int_status & QM_SPI_ISR_TXEIS &&
transfer->tx_len > tx_counter[spi]) {
handle_tx_interrupt(spi);
}
}
