void main() {
setuptriglookup();
allegrosetup(scrwid,scrhei);
makepalette(&greypalette);
mypalette(255,0,0,0);
mypalette(0,0,0,0);
mypalette(255,1,1,1);
mypalette(128,0,0,0);
for (int r=0;r<16;r++) {
for (int g=0;g<16;g++) {
int palc=r+g*16;
mypalette(palc,(r==0?0:brightness+0.2+change*0.5*r/15.0),(g==0?0:brightness+change*0.1+0.2*g/15.0),(g==0?0:brightness+change*0.2+0.6*g/15.0));
// Groovy colours mypalette(palc,(r==0?0:0.1+0.6*r/15.0),(g==0?0:0.1+0.2*g/15.0),(g==0?0:0.1+0.7*g/15.0));
// Good colours: mypalette(palc,(r==0?0:0.3+0.4*r/15.0),(g==0?0:0.1+0.2*g/15.0),(g==0?0:0.3+0.5*g/15.0));
}
}
float pd=2.5;
PPsetup(scrwid,scrhei,pd);
V3d vel=V3d(0,0,0);
V3d acc=V3d(0,0,0);
float droll=0;
float dyaw=0;
float dpitch=0;
int frame=0;
// Set up track
randomise();
for (int i=0;i<=15;i++) {
waves+Wave();
// waves.num(i).display();
}
for (float thru=0;thru<1.0;thru+=1.0/(float)numps) {
V3d here=getpos(thru);
V3d forward=getpos(thru+0.00001)-here;
V3d up=V3d::normcross(V3d::crazy,forward);
V3d right=V3d::normcross(forward,up);
for (int i=0;i<tunnelps;i++) {
float t=2*pi*(float)i/(float)tunnelps;
float s=sin(t);
float c=cos(t);
V3d v=here+tunnelrad*(s*up+c*right);
octree.add(v);
}
}
for (int i=1;i<500;i++) {
octree.add(8.0*V3d(floatrnd(-1,1),floatrnd(-1,1),floatrnd(-1,1)));
}
// Display track
float t=0;
do {
t=t+0.03;
V3d from=V3d::rotate(6.0*V3d::k,V3d::j,t);
ori.forcez(from.neg());
pos=from;
plotscene();
writescreen();
} while (!key[KEY_SPACE]);
do {
} while (key[KEY_SPACE]);
// Race
starttimer();
float thru=0;
float marker=0;
pos=getpos(marker);
V3d *tail=new V3d[taillen];
int tailpos=0;
do {
thru+=0.001;
// V3d last=V3d(pos.x,pos.y,pos.z);
// V3d pos=getpos(thru);
// V3d next=getpos(thru+0.00001);
// V3d newz=next-pos;
// ori.forcez(newz);
frame++;
// float pd=1.6+1.3*sin(2*pi*frame/1000.0);
plotscene();
// Plot and move marker
V3d m;
for (int i=1;i<=15;i++) {
m=V3d::disorientate(getpos(marker)-pos,ori);
if (m.mod()<markerrange)
marker+=0.0002;
}
float u=PPgetunitnoadd(m);
bool plot=false;
if (u) {
int x,y;
float rad=0.12*u;
if (PPgetscrposnoadd(m,PPlefteye,&x,&y))
if (left.inimage(x,y)) {
plot=true;
left.opencircle(x,y,rad,15);
left.opencircle(x,y,rad/2,15);
}
if (PPgetscrposnoadd(m,PPrighteye,&x,&y))
if (right.inimage(x,y)) {
plot=true;
right.opencircle(x,y,rad,15*16);
right.opencircle(x,y,rad/2,15*16);
}
}
if (!plot) {
V2d v=scrwid*2*V2d(m.x,m.y).norm();
if (abs(v.x)>scrwid/2) {
float change=(float)scrwid/2.0/abs(v.x);
v=change*v;
}
if (abs(v.y)>scrhei/2) {
float change=(float)scrhei/2.0/abs(v.y);
v=change*v;
}
v=v+V2d(scrwid/2,scrhei/2);
left.opencircle(v,5,15);
right.opencircle(v,5,15*16);
}
// Pull player towards marker
// if (m.mod()>markerrange+.1) {
V3d pulldir=getpos(marker)-pos;
// vel=vel+pulldir*0.02;
// float amount=(V3d::normdot(ori.z(),pulldir)+5.0)/6.0;
float amount=chop(0.99-(m.mod()-markerrange)/5.0,0,1);
V3d newz=ori.z()*amount+(1.0-amount)*pulldir;
ori.forcez(newz);
// vel=vel*amount;
//
//
// }
// Draw and update tail
V3d last=(tail[tailpos]-pos).disorientate(ori);
for (int k=1;k<taillen;k++) {
int j=mymod(tailpos+k,taillen);
V3d next=(tail[j]-pos).disorientate(ori);
plotline(last,next,(float)k/(float)taillen);
last=next;
}
if ((frame % 2)==0) {
tail[tailpos]=pos-ori.qz;
tailpos=mymod(tailpos+1,taillen);
}
writescreen();
// acc=hang(acc,V3d::origin,0.95,0.01);
// Movement
float angvel=turnability;
if (key[KEY_LCONTROL])
vel=vel+ori.z()*forcevel;
else
angvel=turnability*2.0;
if (key[KEY_DOWN])
dpitch=dpitch+angvel;
if (key[KEY_UP])
dpitch=dpitch-angvel;
if (key[KEY_LEFT])
if (key[KEY_ALT])
droll=droll-angvel;
else
dyaw=dyaw-angvel;
if (key[KEY_RIGHT])
if (key[KEY_ALT])
droll=droll+angvel;
else
dyaw=dyaw+angvel;
vel=hang(vel,V3d::o,0.92,0);
pos=pos+vel;
droll=hang(droll,0,0.9,0);
dyaw=hang(dyaw,0,0.9,0);
dpitch=hang(dpitch,0,0.9,0);
ori.roll(droll/5.0);
ori.yaw(dyaw/5.0);
ori.pitch(dpitch/5.0);
framedone();
} while (!key[KEY_SPACE] && !key[KEY_ESC]);
savetimer();
allegro_exit();
displayframespersecond();
}
void board_init_r(gd_t *dummy1, ulong dummy2)
{
u32 boot_device;
debug(">>spl:board_init_r()\n");
#ifdef CONFIG_SYS_SPL_MALLOC_START
mem_malloc_init(CONFIG_SYS_SPL_MALLOC_START,
CONFIG_SYS_SPL_MALLOC_SIZE);
#endif
#ifndef CONFIG_PPC
/*
* timer_init() does not exist on PPC systems. The timer is initialized
* and enabled (decrementer) in interrupt_init() here.
*/
timer_init();
#endif
#ifdef CONFIG_SPL_BOARD_INIT
spl_board_init();
#endif
boot_device = spl_boot_device();
debug("boot device - %d\n", boot_device);
switch (boot_device) {
#ifdef CONFIG_SPL_RAM_DEVICE
case BOOT_DEVICE_RAM:
spl_ram_load_image();
break;
#endif
#ifdef CONFIG_SPL_MMC_SUPPORT
case BOOT_DEVICE_MMC1:
case BOOT_DEVICE_MMC2:
case BOOT_DEVICE_MMC2_2:
spl_mmc_load_image();
break;
#endif
#ifdef CONFIG_SPL_NAND_SUPPORT
case BOOT_DEVICE_NAND:
spl_nand_load_image();
break;
#endif
#ifdef CONFIG_SPL_ONENAND_SUPPORT
case BOOT_DEVICE_ONENAND:
spl_onenand_load_image();
break;
#endif
#ifdef CONFIG_SPL_NOR_SUPPORT
case BOOT_DEVICE_NOR:
spl_nor_load_image();
break;
#endif
#ifdef CONFIG_SPL_YMODEM_SUPPORT
case BOOT_DEVICE_UART:
spl_ymodem_load_image();
break;
#endif
#ifdef CONFIG_SPL_SPI_SUPPORT
case BOOT_DEVICE_SPI:
spl_spi_load_image();
break;
#endif
#ifdef CONFIG_SPL_ETH_SUPPORT
case BOOT_DEVICE_CPGMAC:
#ifdef CONFIG_SPL_ETH_DEVICE
spl_net_load_image(CONFIG_SPL_ETH_DEVICE);
#else
spl_net_load_image(NULL);
#endif
break;
#endif
#ifdef CONFIG_SPL_USBETH_SUPPORT
case BOOT_DEVICE_USBETH:
spl_net_load_image("usb_ether");
break;
#endif
#ifdef CONFIG_SPL_USB_SUPPORT
case BOOT_DEVICE_USB:
spl_usb_load_image();
break;
#endif
#ifdef CONFIG_SPL_SATA_SUPPORT
case BOOT_DEVICE_SATA:
spl_sata_load_image();
break;
#endif
default:
debug("SPL: Un-supported Boot Device\n");
hang();
}
switch (spl_image.os) {
case IH_OS_U_BOOT:
debug("Jumping to U-Boot\n");
break;
#ifdef CONFIG_SPL_OS_BOOT
case IH_OS_LINUX:
debug("Jumping to Linux\n");
spl_board_prepare_for_linux();
jump_to_image_linux((void *)CONFIG_SYS_SPL_ARGS_ADDR);
#endif
default:
debug("Unsupported OS image.. Jumping nevertheless..\n");
}
jump_to_image_no_args(&spl_image);
}
void board_init (void)
{
bd_t *bd;
init_fnc_t **init_fnc_ptr;
gd = (gd_t *) (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET);
bd = (bd_t *) (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET \
- GENERATED_BD_INFO_SIZE);
char *s;
#if defined(CONFIG_CMD_FLASH)
ulong flash_size = 0;
#endif
asm ("nop"); /* FIXME gd is not initialize - wait */
memset ((void *)gd, 0, GENERATED_GBL_DATA_SIZE);
memset ((void *)bd, 0, GENERATED_BD_INFO_SIZE);
gd->bd = bd;
gd->baudrate = CONFIG_BAUDRATE;
bd->bi_baudrate = CONFIG_BAUDRATE;
bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
/*
* The Malloc area is immediately below the monitor copy in DRAM
* aka CONFIG_SYS_MONITOR_BASE - Note there is no need for reloc_off
* as our monitory code is run from SDRAM
*/
mem_malloc_init (CONFIG_SYS_MALLOC_BASE, CONFIG_SYS_MALLOC_LEN);
for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
WATCHDOG_RESET ();
if ((*init_fnc_ptr) () != 0) {
hang ();
}
}
puts ("SDRAM :\n");
printf ("\t\tIcache:%s\n", icache_status() ? "ON" : "OFF");
printf ("\t\tDcache:%s\n", dcache_status() ? "ON" : "OFF");
printf ("\tU-Boot Start:0x%08x\n", CONFIG_SYS_TEXT_BASE);
#if defined(CONFIG_CMD_FLASH)
puts ("FLASH: ");
bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
if (0 < (flash_size = flash_init ())) {
bd->bi_flashsize = flash_size;
bd->bi_flashoffset = CONFIG_SYS_FLASH_BASE + flash_size;
# ifdef CONFIG_SYS_FLASH_CHECKSUM
print_size (flash_size, "");
/*
* Compute and print flash CRC if flashchecksum is set to 'y'
*
* NOTE: Maybe we should add some WATCHDOG_RESET()? XXX
*/
s = getenv ("flashchecksum");
if (s && (*s == 'y')) {
printf (" CRC: %08X",
crc32 (0, (const unsigned char *) CONFIG_SYS_FLASH_BASE, flash_size)
);
}
putc ('\n');
# else /* !CONFIG_SYS_FLASH_CHECKSUM */
print_size (flash_size, "\n");
# endif /* CONFIG_SYS_FLASH_CHECKSUM */
} else {
puts ("Flash init FAILED");
bd->bi_flashstart = 0;
bd->bi_flashsize = 0;
bd->bi_flashoffset = 0;
}
#endif
/* relocate environment function pointers etc. */
env_relocate ();
/* Initialize stdio devices */
stdio_init ();
if ((s = getenv ("loadaddr")) != NULL) {
load_addr = simple_strtoul (s, NULL, 16);
}
#if defined(CONFIG_CMD_NET)
/* IP Address */
bd->bi_ip_addr = getenv_IPaddr("ipaddr");
printf("Net: ");
eth_initialize(gd->bd);
uchar enetaddr[6];
eth_getenv_enetaddr("ethaddr", enetaddr);
printf("MAC: %pM\n", enetaddr);
#endif
/* main_loop */
for (;;) {
WATCHDOG_RESET ();
main_loop ();
}
}
void board_init_f(ulong bootflag)
{
bd_t *bd;
init_fnc_t **init_fnc_ptr;
gd_t *id;
ulong addr, addr_sp;
#ifdef CONFIG_PRAM
ulong reg;
#endif
void *new_fdt = NULL;
size_t fdt_size = 0;
memset((void *)gd, 0, sizeof(gd_t));
gd->mon_len = _bss_end_ofs;
#ifdef CONFIG_OF_EMBED
/* Get a pointer to the FDT */
gd->fdt_blob = _binary_dt_dtb_start;
#elif defined CONFIG_OF_SEPARATE
/* FDT is at end of image */
gd->fdt_blob = (void *)(_end_ofs + _TEXT_BASE);
#endif
/* Allow the early environment to override the fdt address */
gd->fdt_blob = (void *)getenv_ulong("fdtcontroladdr", 16,
(uintptr_t)gd->fdt_blob);
for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
if ((*init_fnc_ptr)() != 0) {
hang ();
}
}
#ifdef CONFIG_OF_CONTROL
/* For now, put this check after the console is ready */
if (fdtdec_prepare_fdt()) {
panic("** CONFIG_OF_CONTROL defined but no FDT - please see "
"doc/README.fdt-control");
}
#endif
debug("monitor len: %08lX\n", gd->mon_len);
/*
* Ram is setup, size stored in gd !!
*/
debug("ramsize: %08lX\n", gd->ram_size);
#if defined(CONFIG_SYS_MEM_TOP_HIDE)
/*
* Subtract specified amount of memory to hide so that it won't
* get "touched" at all by U-Boot. By fixing up gd->ram_size
* the Linux kernel should now get passed the now "corrected"
* memory size and won't touch it either. This should work
* for arch/ppc and arch/powerpc. Only Linux board ports in
* arch/powerpc with bootwrapper support, that recalculate the
* memory size from the SDRAM controller setup will have to
* get fixed.
*/
gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE;
#endif
addr = CONFIG_SYS_SDRAM_BASE + gd->ram_size;
#ifdef CONFIG_LOGBUFFER
#ifndef CONFIG_ALT_LB_ADDR
/* reserve kernel log buffer */
addr -= (LOGBUFF_RESERVE);
debug("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN,
addr);
#endif
#endif
#ifdef CONFIG_PRAM
/*
* reserve protected RAM
*/
reg = getenv_ulong("pram", 10, CONFIG_PRAM);
addr -= (reg << 10); /* size is in kB */
debug("Reserving %ldk for protected RAM at %08lx\n", reg, addr);
#endif /* CONFIG_PRAM */
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
/* reserve TLB table */
gd->arch.tlb_size = 4096 * 4;
addr -= gd->arch.tlb_size;
/* round down to next 64 kB limit */
addr &= ~(0x10000 - 1);
gd->arch.tlb_addr = addr;
debug("TLB table from %08lx to %08lx\n", addr, addr + gd->arch.tlb_size);
#endif
/* round down to next 4 kB limit */
addr &= ~(4096 - 1);
debug("Top of RAM usable for U-Boot at: %08lx\n", addr);
#ifdef CONFIG_LCD
#ifdef CONFIG_FB_ADDR
gd->fb_base = CONFIG_FB_ADDR;
#else
/* reserve memory for LCD display (always full pages) */
addr = lcd_setmem(addr);
gd->fb_base = addr;
#endif /* CONFIG_FB_ADDR */
#endif /* CONFIG_LCD */
/*
* reserve memory for U-Boot code, data & bss
* round down to next 4 kB limit
*/
addr -= gd->mon_len;
addr &= ~(4096 - 1);
debug("Reserving %ldk for U-Boot at: %08lx\n", gd->mon_len >> 10, addr);
#ifndef CONFIG_SPL_BUILD
/*
* reserve memory for malloc() arena
*/
addr_sp = addr - TOTAL_MALLOC_LEN;
debug("Reserving %dk for malloc() at: %08lx\n",
TOTAL_MALLOC_LEN >> 10, addr_sp);
/*
* (permanently) allocate a Board Info struct
* and a permanent copy of the "global" data
*/
addr_sp -= sizeof (bd_t);
bd = (bd_t *) addr_sp;
gd->bd = bd;
debug("Reserving %zu Bytes for Board Info at: %08lx\n",
sizeof (bd_t), addr_sp);
#ifdef CONFIG_MACH_TYPE
gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */
#endif
addr_sp -= sizeof (gd_t);
id = (gd_t *) addr_sp;
debug("Reserving %zu Bytes for Global Data at: %08lx\n",
sizeof (gd_t), addr_sp);
#if defined(CONFIG_OF_SEPARATE) && defined(CONFIG_OF_CONTROL)
/*
* If the device tree is sitting immediate above our image then we
* must relocate it. If it is embedded in the data section, then it
* will be relocated with other data.
*/
if (gd->fdt_blob) {
fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32);
addr_sp -= fdt_size;
new_fdt = (void *)addr_sp;
debug("Reserving %zu Bytes for FDT at: %08lx\n",
fdt_size, addr_sp);
}
#endif
/* setup stackpointer for exeptions */
gd->irq_sp = addr_sp;
#ifdef CONFIG_USE_IRQ
addr_sp -= (CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ);
debug("Reserving %zu Bytes for IRQ stack at: %08lx\n",
CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ, addr_sp);
#endif
/* leave 3 words for abort-stack */
addr_sp -= 12;
/* 8-byte alignment for ABI compliance */
addr_sp &= ~0x07;
#else
addr_sp += 128; /* leave 32 words for abort-stack */
gd->irq_sp = addr_sp;
#endif
debug("New Stack Pointer is: %08lx\n", addr_sp);
#ifdef CONFIG_POST
post_bootmode_init();
post_run(NULL, POST_ROM | post_bootmode_get(0));
#endif
gd->bd->bi_baudrate = gd->baudrate;
/* Ram ist board specific, so move it to board code ... */
dram_init_banksize();
display_dram_config(); /* and display it */
gd->relocaddr = addr;
gd->start_addr_sp = addr_sp;
gd->reloc_off = addr - _TEXT_BASE;
debug("relocation Offset is: %08lx\n", gd->reloc_off);
if (new_fdt) {
memcpy(new_fdt, gd->fdt_blob, fdt_size);
gd->fdt_blob = new_fdt;
}
memcpy(id, (void *)gd, sizeof(gd_t));
}
/*
* spl_boot:
*
* All supported booting types of all supported SoCs are listed here.
* Generic readback APIs are provided for each supported booting type
* eg. nand_read_skip_bad
*/
u32 spl_boot(void)
{
void (*image)(void);
#ifdef CONFIG_SPEAR_USBTTY
plat_late_init();
return 1;
#endif
/*
* All the supported booting devices are listed here. Each of
* the booting type supported by the platform would define the
* macro xxx_BOOT_SUPPORTED to TRUE.
*/
if (SNOR_BOOT_SUPPORTED && snor_boot_selected()) {
/* SNOR-SMI initialization */
snor_init();
serial_puts("Booting via SNOR\n");
/* Serial NOR booting */
if (1 == snor_image_load((u8 *)CONFIG_SYS_UBOOT_BASE,
&image, loader_name)) {
/* Platform related late initialasations */
plat_late_init();
/* Jump to boot image */
serial_puts("Jumping to U-Boot\n");
boot_image(image);
return 1;
}
}
if (NAND_BOOT_SUPPORTED && nand_boot_selected()) {
/* NAND booting */
/* Not ported from XLoader to SPL yet */
return 0;
}
if (PNOR_BOOT_SUPPORTED && pnor_boot_selected()) {
/* PNOR booting */
/* Not ported from XLoader to SPL yet */
return 0;
}
if (MMC_BOOT_SUPPORTED && mmc_boot_selected()) {
/* MMC booting */
/* Not ported from XLoader to SPL yet */
return 0;
}
if (SPI_BOOT_SUPPORTED && spi_boot_selected()) {
/* SPI booting */
/* Not supported for any platform as of now */
return 0;
}
if (I2C_BOOT_SUPPORTED && i2c_boot_selected()) {
/* I2C booting */
/* Not supported for any platform as of now */
return 0;
}
/*
* All booting types without memory are listed as below
* Control has to be returned to BootROM in case of all
* the following booting scenarios
*/
if (USB_BOOT_SUPPORTED && usb_boot_selected()) {
plat_late_init();
return 1;
}
if (TFTP_BOOT_SUPPORTED && tftp_boot_selected()) {
plat_late_init();
return 1;
}
if (UART_BOOT_SUPPORTED && uart_boot_selected()) {
plat_late_init();
return 1;
}
/* Ideally, the control should not reach here. */
hang();
}
static void mem_remap(void)
{
uint32_t start = 0, num = 0;
int row, col, dw32, bank8, cs0, cs1;
uint32_t size0 = 0, size1 = 0;
#ifdef CONFIG_DDR_HOST_CC
#if (CONFIG_DDR_CS0 == 1)
row = DDR_ROW;
col = DDR_COL;
dw32 = CONFIG_DDR_DW32;
bank8 = DDR_BANK8;
#endif
size0 = (unsigned int)(DDR_CHIP_0_SIZE);
size1 = (unsigned int)(DDR_CHIP_1_SIZE);
/* For two different size ddr chips, just don't remmap */
#if (CONFIG_DDR_CS1 == 1)
if (size0 != size1)
return;
#endif
#if (CONFIG_DDR_CS0 == 1)
#if (CONFIG_DDR_CS1 == 1)
if (size1 && size0) {
if (size1 <= size0) {
row = DDR_ROW1;
col = DDR_COL1;
dw32 = CONFIG_DDR_DW32;
bank8 = DDR_BANK8;
} else {
row = DDR_ROW;
col = DDR_COL;
dw32 = CONFIG_DDR_DW32;
bank8 = DDR_BANK8;
}
} else {
printf("Error: The DDR size is 0\n");
hang();
}
#else /*CONFIG_DDR_CS1 == 1*/
if (size0) {
row = DDR_ROW;
col = DDR_COL;
dw32 = CONFIG_DDR_DW32;
bank8 = DDR_BANK8;
} else {
printf("Error: The DDR size is 0\n");
hang();
}
#endif /* CONFIG_DDR_CS1 == 1 */
#else /* CONFIG_DDR_CS0 == 1 */
if (size1) {
row = DDR_ROW1;
col = DDR_COL1;
dw32 = CONFIG_DDR_DW32;
bank8 = DDR_BANK8;
} else {
printf("Error: The DDR size is 0\n");
hang();
}
#endif /* CONFIG_DDR_CS0 == 1 */
cs0 = CONFIG_DDR_CS0;
cs1 = CONFIG_DDR_CS1;
#else /* CONFIG_DDR_HOST_CC */
size0 = ddr_params_p->size.chip0;
size1 = ddr_params_p->size.chip1;
if (size0 && size1) {
if (size1 <= size0) {
row = ddr_params_p->row1;
col = ddr_params_p->col1;
dw32 = ddr_params_p->dw32;
bank8 = ddr_params_p->bank8;
} else {
row = ddr_params_p->row;
col = ddr_params_p->col;
dw32 = ddr_params_p->dw32;
bank8 = ddr_params_p->bank8;
}
} else if (size0) {
row = ddr_params_p->row;
col = ddr_params_p->col;
dw32 = ddr_params_p->dw32;
bank8 = ddr_params_p->bank8;
} else if (size1) {
row = ddr_params_p->row1;
col = ddr_params_p->col1;
dw32 = ddr_params_p->dw32;
bank8 = ddr_params_p->bank8;
} else {
printf("Error: The DDR size is 0\n");
hang();
}
cs0 = ddr_params_p->cs0;
cs1 = ddr_params_p->cs1;
#endif /* CONFIG_DDR_HOST_CC */
start += row + col + (dw32 ? 4 : 2) / 2;
start -= 12;
if (bank8)
num += 3;
else
num += 2;
if (cs0 && cs1)
num++;
for (; num > 0; num--)
remap_swap(0 + num - 1, start + num - 1);
}
void main() {
allegrosetup(scrwid,scrhei);
makepalette(&greypalette);
mypalette(255,0,0,0);
mypalette(0,0,0,0);
mypalette(255,1,1,1);
mypalette(128,0,0,0);
for (int r=0;r<8;r++) {
for (int g=0;g<8;g++) {
int palc=r+g*8;
mypalette(palc,(r==0?0:0.3+0.4*r/7.0),(g==0?0:0.1+0.2*g/7.0),(g==0?0:0.3+0.5*g/7.0));
}
}
// randomise();
V3d pos=V3d(0,0,0);
V3d vel=V3d(0,0,0);
V3d acc=V3d(0,0,0);
Ori ori;
float droll=0;
float dyaw=0;
float roll=0;
float yaw=0;
float pitch=0;
int frame=0;
starttimer();
do {
frame++;
float pd=2.0+1.8*sin(2*pi*frame/1000.0);
PPsetup(scrwid,scrhei,pd);
left.clear(0);
right.clear(0);
// b.fadeby(16);
V3d off=V3d(mymod(pos.x,gjump),mymod(pos.y,gjump),mymod(pos.z,gjump));
int ioff=-mydiv(pos.x,gjump);
int joff=-mydiv(pos.y,gjump);
int koff=-mydiv(pos.z,gjump);
ori.quickorisetup();
// Need to find largest axis, and do loops with that one outside
int ks=mysgn(ori.qz.z);
int js=-mysgn(ori.qz.y);
int is=-mysgn(ori.qz.x);
for (int k=ks*gridsize;k!=-ks*gridsize;k=k-ks*gjump)
for (int i=-is*gridsize;i!=is*gridsize;i=i+is*gjump)
for (int j=-js*gridsize;j!=js*gridsize;j=j+js*gjump) {
int x,y;
V3d cen=V3d(i,j,k)-off;
cen=V3d::qorientate(cen,ori);
int c=7-chop(7*(cen.z+pd+1)/(gridsize+2),0,7);
plotsphere(cen,c);
}
for (int i=0;i<scrwid;i++) {
for (int j=0;j<scrhei;j++) {
b.bmp[j][i]=(left.bmp[j][i] | right.bmp[j][i]);
}
}
b.writetoscreen();
acc=hang(acc,V3d::origin,0.95,0.01);
vel=hang(vel,ori.qz/10,0.94,0)+acc;
pos=pos+vel;
droll=hang(droll,0,0.9,0.01);
dyaw=hang(dyaw,0,0.95,0.01);
roll=hang(roll,0,0.95,0)+droll;
yaw=hang(yaw,0,0.92,0)+dyaw;
pitch=hang(pitch,0,0.999,0.01);
pos=pos+ori.qz*4;
ori.roll(roll/5.0);
ori.yaw(yaw/5.0);
pos=pos-ori.z()*4;
framedone();
} while (!key[KEY_SPACE] && !key[KEY_ESC]);
savetimer();
allegro_exit();
displayframespersecond();
}
float hang(float *x,float cen,float damp) {
*x=hang(*x,cen,damp,0);
}
static float hang(float x,float cen,float damp,float rnd) {
return hang(x,cen,damp,rnd);
}
/*
* This is the next part if the initialization sequence: we are now
* running from RAM and have a "normal" C environment, i. e. global
* data can be written, BSS has been cleared, the stack size in not
* that critical any more, etc.
*/
void board_init_r(gd_t *id, ulong dest_addr)
{
bd_t *bd;
ulong malloc_start;
#ifndef CONFIG_SYS_NO_FLASH
ulong flash_size;
#endif
gd = id; /* initialize RAM version of global data */
bd = gd->bd;
gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
/* The Malloc area is immediately below the monitor copy in DRAM */
malloc_start = dest_addr - TOTAL_MALLOC_LEN;
#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
/*
* The gd->arch.cpu pointer is set to an address in flash before
* relocation. We need to update it to point to the same CPU entry
* in RAM.
*/
gd->arch.cpu += dest_addr - CONFIG_SYS_MONITOR_BASE;
/*
* If we didn't know the cpu mask & # cores, we can save them of
* now rather than 'computing' them constantly
*/
fixup_cpu();
#endif
#ifdef CONFIG_SYS_EXTRA_ENV_RELOC
/*
* Some systems need to relocate the env_addr pointer early because the
* location it points to will get invalidated before env_relocate is
* called. One example is on systems that might use a L2 or L3 cache
* in SRAM mode and initialize that cache from SRAM mode back to being
* a cache in cpu_init_r.
*/
gd->env_addr += dest_addr - CONFIG_SYS_MONITOR_BASE;
#endif
serial_initialize();
debug("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
WATCHDOG_RESET();
/*
* Setup trap handlers
*/
trap_init(dest_addr);
#ifdef CONFIG_ADDR_MAP
init_addr_map();
#endif
#if defined(CONFIG_BOARD_EARLY_INIT_R)
board_early_init_r();
#endif
monitor_flash_len = (ulong)&__init_end - dest_addr;
WATCHDOG_RESET();
#ifdef CONFIG_LOGBUFFER
logbuff_init_ptrs();
#endif
#ifdef CONFIG_POST
post_output_backlog();
#endif
WATCHDOG_RESET();
#if defined(CONFIG_SYS_DELAYED_ICACHE)
icache_enable(); /* it's time to enable the instruction cache */
#endif
#if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500)
unlock_ram_in_cache(); /* it's time to unlock D-cache in e500 */
#endif
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_EARLY_PCI_INIT)
/*
* Do early PCI configuration _before_ the flash gets initialised,
* because PCU ressources are crucial for flash access on some boards.
*/
pci_init();
#endif
#if defined(CONFIG_WINBOND_83C553)
/*
* Initialise the ISA bridge
*/
initialise_w83c553f();
#endif
asm("sync ; isync");
mem_malloc_init(malloc_start, TOTAL_MALLOC_LEN);
#if !defined(CONFIG_SYS_NO_FLASH)
puts("Flash: ");
if (board_flash_wp_on()) {
printf("Uninitialized - Write Protect On\n");
/* Since WP is on, we can't find real size. Set to 0 */
flash_size = 0;
} else if ((flash_size = flash_init()) > 0) {
#ifdef CONFIG_SYS_FLASH_CHECKSUM
print_size(flash_size, "");
/*
* Compute and print flash CRC if flashchecksum is set to 'y'
*
* NOTE: Maybe we should add some WATCHDOG_RESET()? XXX
*/
if (getenv_yesno("flashchecksum") == 1) {
printf(" CRC: %08X",
crc32(0,
(const unsigned char *)
CONFIG_SYS_FLASH_BASE, flash_size)
);
}
putc('\n');
#else /* !CONFIG_SYS_FLASH_CHECKSUM */
print_size(flash_size, "\n");
#endif /* CONFIG_SYS_FLASH_CHECKSUM */
} else {
puts(failed);
hang();
}
/* update start of FLASH memory */
bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
/* size of FLASH memory (final value) */
bd->bi_flashsize = flash_size;
#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
/* Make a update of the Memctrl. */
update_flash_size(flash_size);
#endif
#if defined(CONFIG_OXC) || defined(CONFIG_RMU)
/* flash mapped at end of memory map */
bd->bi_flashoffset = CONFIG_SYS_TEXT_BASE + flash_size;
#elif CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE
bd->bi_flashoffset = monitor_flash_len; /* reserved area for monitor */
#endif
#endif /* !CONFIG_SYS_NO_FLASH */
WATCHDOG_RESET();
/* initialize higher level parts of CPU like time base and timers */
cpu_init_r();
WATCHDOG_RESET();
#ifdef CONFIG_SPI
#if !defined(CONFIG_ENV_IS_IN_EEPROM)
spi_init_f();
#endif
spi_init_r();
#endif
#if defined(CONFIG_CMD_NAND)
WATCHDOG_RESET();
puts("NAND: ");
nand_init(); /* go init the NAND */
#endif
#ifdef CONFIG_GENERIC_MMC
/*
* MMC initialization is called before relocating env.
* Thus It is required that operations like pin multiplexer
* be put in board_init.
*/
WATCHDOG_RESET();
puts("MMC: ");
mmc_initialize(bd);
#endif
/* relocate environment function pointers etc. */
env_relocate();
/*
* after non-volatile devices & environment is setup and cpu code have
* another round to deal with any initialization that might require
* full access to the environment or loading of some image (firmware)
* from a non-volatile device
*/
cpu_secondary_init_r();
/*
* Fill in missing fields of bd_info.
* We do this here, where we have "normal" access to the
* environment; we used to do this still running from ROM,
* where had to use getenv_f(), which can be pretty slow when
* the environment is in EEPROM.
*/
#if defined(CONFIG_SYS_EXTBDINFO)
#if defined(CONFIG_405GP) || defined(CONFIG_405EP)
#if defined(CONFIG_I2CFAST)
/*
* set bi_iic_fast for linux taking environment variable
* "i2cfast" into account
*/
{
if (getenv_yesno("i2cfast") == 1) {
bd->bi_iic_fast[0] = 1;
bd->bi_iic_fast[1] = 1;
}
}
#endif /* CONFIG_I2CFAST */
#endif /* CONFIG_405GP, CONFIG_405EP */
#endif /* CONFIG_SYS_EXTBDINFO */
#if defined(CONFIG_SC3)
sc3_read_eeprom();
#endif
#if defined(CONFIG_ID_EEPROM) || defined(CONFIG_SYS_I2C_MAC_OFFSET)
mac_read_from_eeprom();
#endif
#ifdef CONFIG_CMD_NET
/* kept around for legacy kernels only ... ignore the next section */
eth_getenv_enetaddr("ethaddr", bd->bi_enetaddr);
#ifdef CONFIG_HAS_ETH1
eth_getenv_enetaddr("eth1addr", bd->bi_enet1addr);
#endif
#ifdef CONFIG_HAS_ETH2
eth_getenv_enetaddr("eth2addr", bd->bi_enet2addr);
#endif
#ifdef CONFIG_HAS_ETH3
eth_getenv_enetaddr("eth3addr", bd->bi_enet3addr);
#endif
#ifdef CONFIG_HAS_ETH4
eth_getenv_enetaddr("eth4addr", bd->bi_enet4addr);
#endif
#ifdef CONFIG_HAS_ETH5
eth_getenv_enetaddr("eth5addr", bd->bi_enet5addr);
#endif
#endif /* CONFIG_CMD_NET */
WATCHDOG_RESET();
#if defined(CONFIG_PCI) && !defined(CONFIG_SYS_EARLY_PCI_INIT)
/*
* Do pci configuration
*/
pci_init();
#endif
/** leave this here (after malloc(), environment and PCI are working) **/
/* Initialize stdio devices */
stdio_init();
/* Initialize the jump table for applications */
jumptable_init();
#if defined(CONFIG_API)
/* Initialize API */
api_init();
#endif
/* Initialize the console (after the relocation and devices init) */
console_init_r();
#if defined(CONFIG_MISC_INIT_R)
/* miscellaneous platform dependent initialisations */
misc_init_r();
#endif
#if defined(CONFIG_CMD_KGDB)
WATCHDOG_RESET();
puts("KGDB: ");
kgdb_init();
#endif
debug("U-Boot relocated to %08lx\n", dest_addr);
/*
* Enable Interrupts
*/
interrupt_init();
#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
status_led_set(STATUS_LED_BOOT, STATUS_LED_BLINKING);
#endif
udelay(20);
/* Initialize from environment */
load_addr = getenv_ulong("loadaddr", 16, load_addr);
WATCHDOG_RESET();
#if defined(CONFIG_CMD_SCSI)
WATCHDOG_RESET();
puts("SCSI: ");
scsi_init();
#endif
#if defined(CONFIG_CMD_DOC)
WATCHDOG_RESET();
puts("DOC: ");
doc_init();
#endif
#ifdef CONFIG_BITBANGMII
bb_miiphy_init();
#endif
#if defined(CONFIG_CMD_NET)
WATCHDOG_RESET();
puts("Net: ");
eth_initialize();
#endif
#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
WATCHDOG_RESET();
debug("Reset Ethernet PHY\n");
reset_phy();
#endif
#ifdef CONFIG_POST
post_run(NULL, POST_RAM | post_bootmode_get(0));
#endif
#if defined(CONFIG_CMD_PCMCIA) \
&& !defined(CONFIG_CMD_IDE)
WATCHDOG_RESET();
puts("PCMCIA:");
pcmcia_init();
#endif
#if defined(CONFIG_CMD_IDE)
WATCHDOG_RESET();
#ifdef CONFIG_IDE_8xx_PCCARD
puts("PCMCIA:");
#else
puts("IDE: ");
#endif
#if defined(CONFIG_START_IDE)
if (board_start_ide())
ide_init();
#else
ide_init();
#endif
#endif
#ifdef CONFIG_LAST_STAGE_INIT
WATCHDOG_RESET();
/*
* Some parts can be only initialized if all others (like
* Interrupts) are up and running (i.e. the PC-style ISA
* keyboard).
*/
last_stage_init();
#endif
#if defined(CONFIG_CMD_BEDBUG)
WATCHDOG_RESET();
bedbug_init();
#endif
#if defined(CONFIG_PRAM) || defined(CONFIG_LOGBUFFER)
/*
* Export available size of memory for Linux,
* taking into account the protected RAM at top of memory
*/
{
ulong pram = 0;
char memsz[32];
#ifdef CONFIG_PRAM
pram = getenv_ulong("pram", 10, CONFIG_PRAM);
#endif
#ifdef CONFIG_LOGBUFFER
#ifndef CONFIG_ALT_LB_ADDR
/* Also take the logbuffer into account (pram is in kB) */
pram += (LOGBUFF_LEN + LOGBUFF_OVERHEAD) / 1024;
#endif
#endif
sprintf(memsz, "%ldk", (ulong) (bd->bi_memsize / 1024) - pram);
setenv("mem", memsz);
}
#endif
#ifdef CONFIG_PS2KBD
puts("PS/2: ");
kbd_init();
#endif
/* Initialization complete - start the monitor */
/* main_loop() can return to retry autoboot, if so just run it again. */
for (;;) {
WATCHDOG_RESET();
main_loop();
}
/* NOTREACHED - no way out of command loop except booting */
}
float hang(float *x,float cen,float damp,float rnd) {
*x=hang(*x,cen,damp,rnd);
}
void board_init_f(ulong bootflag)
{
bd_t *bd;
ulong len, addr, addr_sp;
ulong *s;
gd_t *id;
init_fnc_t **init_fnc_ptr;
#ifdef CONFIG_PRAM
ulong reg;
#endif
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
/* compiler optimization barrier needed for GCC >= 3.4 */
__asm__ __volatile__("":::"memory");
#if !defined(CONFIG_CPM2) && !defined(CONFIG_MPC512X) && \
!defined(CONFIG_MPC83xx) && !defined(CONFIG_MPC85xx) && \
!defined(CONFIG_MPC86xx)
/* Clear initial global data */
memset((void *) gd, 0, sizeof(gd_t));
#endif
gd->flags = bootflag;
for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr)
if ((*init_fnc_ptr) () != 0)
hang();
#ifdef CONFIG_POST
post_bootmode_init();
post_run(NULL, POST_ROM | post_bootmode_get(NULL));
#endif
WATCHDOG_RESET();
/*
* Now that we have DRAM mapped and working, we can
* relocate the code and continue running from DRAM.
*
* Reserve memory at end of RAM for (top down in that order):
* - area that won't get touched by U-Boot and Linux (optional)
* - kernel log buffer
* - protected RAM
* - LCD framebuffer
* - monitor code
* - board info struct
*/
len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE;
/*
* Subtract specified amount of memory to hide so that it won't
* get "touched" at all by U-Boot. By fixing up gd->ram_size
* the Linux kernel should now get passed the now "corrected"
* memory size and won't touch it either. This should work
* for arch/ppc and arch/powerpc. Only Linux board ports in
* arch/powerpc with bootwrapper support, that recalculate the
* memory size from the SDRAM controller setup will have to
* get fixed.
*/
gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE;
addr = CONFIG_SYS_SDRAM_BASE + get_effective_memsize();
#if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500))
/*
* We need to make sure the location we intend to put secondary core
* boot code is reserved and not used by any part of u-boot
*/
if (addr > determine_mp_bootpg(NULL)) {
addr = determine_mp_bootpg(NULL);
debug("Reserving MP boot page to %08lx\n", addr);
}
#endif
#ifdef CONFIG_LOGBUFFER
#ifndef CONFIG_ALT_LB_ADDR
/* reserve kernel log buffer */
addr -= (LOGBUFF_RESERVE);
debug("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN,
addr);
#endif
#endif
#ifdef CONFIG_PRAM
/*
* reserve protected RAM
*/
reg = getenv_ulong("pram", 10, CONFIG_PRAM);
addr -= (reg << 10); /* size is in kB */
debug("Reserving %ldk for protected RAM at %08lx\n", reg, addr);
#endif /* CONFIG_PRAM */
/* round down to next 4 kB limit */
addr &= ~(4096 - 1);
debug("Top of RAM usable for U-Boot at: %08lx\n", addr);
#ifdef CONFIG_LCD
#ifdef CONFIG_FB_ADDR
gd->fb_base = CONFIG_FB_ADDR;
#else
/* reserve memory for LCD display (always full pages) */
addr = lcd_setmem(addr);
gd->fb_base = addr;
#endif /* CONFIG_FB_ADDR */
#endif /* CONFIG_LCD */
#if defined(CONFIG_VIDEO) && defined(CONFIG_8xx)
/* reserve memory for video display (always full pages) */
addr = video_setmem(addr);
gd->fb_base = addr;
#endif /* CONFIG_VIDEO */
/*
* reserve memory for U-Boot code, data & bss
* round down to next 4 kB limit
*/
addr -= len;
addr &= ~(4096 - 1);
#ifdef CONFIG_E500
/* round down to next 64 kB limit so that IVPR stays aligned */
addr &= ~(65536 - 1);
#endif
debug("Reserving %ldk for U-Boot at: %08lx\n", len >> 10, addr);
/*
* reserve memory for malloc() arena
*/
addr_sp = addr - TOTAL_MALLOC_LEN;
debug("Reserving %dk for malloc() at: %08lx\n",
TOTAL_MALLOC_LEN >> 10, addr_sp);
/*
* (permanently) allocate a Board Info struct
* and a permanent copy of the "global" data
*/
addr_sp -= sizeof(bd_t);
bd = (bd_t *) addr_sp;
memset(bd, 0, sizeof(bd_t));
gd->bd = bd;
debug("Reserving %zu Bytes for Board Info at: %08lx\n",
sizeof(bd_t), addr_sp);
addr_sp -= sizeof(gd_t);
id = (gd_t *) addr_sp;
debug("Reserving %zu Bytes for Global Data at: %08lx\n",
sizeof(gd_t), addr_sp);
/*
* Finally, we set up a new (bigger) stack.
*
* Leave some safety gap for SP, force alignment on 16 byte boundary
* Clear initial stack frame
*/
addr_sp -= 16;
addr_sp &= ~0xF;
s = (ulong *) addr_sp;
*s = 0; /* Terminate back chain */
*++s = 0; /* NULL return address */
debug("Stack Pointer at: %08lx\n", addr_sp);
/*
* Save local variables to board info struct
*/
bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */
bd->bi_memsize = gd->ram_size; /* size in bytes */
#ifdef CONFIG_SYS_SRAM_BASE
bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */
bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */
#endif
#if defined(CONFIG_8xx) || defined(CONFIG_MPC8260) || defined(CONFIG_5xx) || \
defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */
#endif
#if defined(CONFIG_MPC5xxx)
bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */
#endif
#if defined(CONFIG_MPC83xx)
bd->bi_immrbar = CONFIG_SYS_IMMR;
#endif
WATCHDOG_RESET();
bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */
bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */
#if defined(CONFIG_CPM2)
bd->bi_cpmfreq = gd->arch.cpm_clk;
bd->bi_brgfreq = gd->arch.brg_clk;
bd->bi_sccfreq = gd->arch.scc_clk;
bd->bi_vco = gd->arch.vco_out;
#endif /* CONFIG_CPM2 */
#if defined(CONFIG_MPC512X)
bd->bi_ipsfreq = gd->arch.ips_clk;
#endif /* CONFIG_MPC512X */
#if defined(CONFIG_MPC5xxx)
bd->bi_ipbfreq = gd->arch.ipb_clk;
bd->bi_pcifreq = gd->pci_clk;
#endif /* CONFIG_MPC5xxx */
#ifdef CONFIG_SYS_EXTBDINFO
strncpy((char *) bd->bi_s_version, "1.2", sizeof(bd->bi_s_version));
strncpy((char *) bd->bi_r_version, U_BOOT_VERSION,
sizeof(bd->bi_r_version));
bd->bi_procfreq = gd->cpu_clk; /* Processor Speed, In Hz */
bd->bi_plb_busfreq = gd->bus_clk;
#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \
defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
bd->bi_pci_busfreq = get_PCI_freq();
bd->bi_opbfreq = get_OPB_freq();
#elif defined(CONFIG_XILINX_405)
bd->bi_pci_busfreq = get_PCI_freq();
#endif
#endif
debug("New Stack Pointer is: %08lx\n", addr_sp);
WATCHDOG_RESET();
gd->relocaddr = addr; /* Store relocation addr, useful for debug */
memcpy(id, (void *) gd, sizeof(gd_t));
relocate_code(addr_sp, id, addr);
/* NOTREACHED - relocate_code() does not return */
}
static
int
lamebus_controller_fetch_config(unsigned cpunum,
int isold, uint32_t offset, uint32_t *ret)
{
const struct lamebus_device_info *inf;
uint32_t region;
lamebus_controller_region(offset, ®ion, &offset);
inf = devices[region].ls_info;
switch (offset) {
case LBC_CONFIG_VENDORID:
*ret = inf ? inf->ldi_vendorid : 0;
return 0;
case LBC_CONFIG_DEVICEID:
*ret = inf ? inf->ldi_deviceid : 0;
return 0;
case LBC_CONFIG_REVISION:
*ret = inf ? inf->ldi_revision : 0;
return 0;
}
if (region != LAMEBUS_CONTROLLER_SLOT) {
return -1;
}
switch (offset) {
case LBC_CTL_RAMSIZE:
*ret = bus_ramsize;
return 0;
case LBC_CTL_IRQS:
*ret = bus_raised_interrupts;
return 0;
case LBC_CTL_POWER:
if (isold) {
hang("Read from LAMEbus controller power register");
*ret = 0;
}
else {
*ret = 0xffffffff;
}
return 0;
case LBC_CTL_IRQE:
*ret = bus_enabled_interrupts;
return 0;
case LBC_CTL_CPUS:
if (isold) {
return -1;
}
if (ncpus == 32) {
/* avoid nasal demons */
*ret = 0xffffffff;
}
else {
*ret = ((uint32_t)1 << ncpus) - 1;
}
return 0;
case LBC_CTL_CPUE:
if (isold) {
return -1;
}
*ret = get_cpue();
return 0;
case LBC_CTL_SELF:
if (isold) {
return -1;
}
*ret = (uint32_t)1 << cpunum;
return 0;
}
return -1;
}
static void mxs_power_init_4p2_regulator(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t tmp, tmp2;
setbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_4P2);
writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_set);
writel(POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
&power_regs->hw_power_5vctrl_clr);
clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_TRG_MASK);
/* Power up the 4p2 rail and logic/control */
writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
&power_regs->hw_power_5vctrl_clr);
/*
* Start charging up the 4p2 capacitor. We ramp of this charge
* gradually to avoid large inrush current from the 5V cable which can
* cause transients/problems
*/
mxs_enable_4p2_dcdc_input(0);
if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
/*
* If we arrived here, we were unable to recover from mx23 chip
* errata 5837. 4P2 is disabled and sufficient battery power is
* not present. Exiting to not enable DCDC power during 5V
* connected state.
*/
clrbits_le32(&power_regs->hw_power_dcdc4p2,
POWER_DCDC4P2_ENABLE_DCDC);
writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
&power_regs->hw_power_5vctrl_set);
hang();
}
/*
* Here we set the 4p2 brownout level to something very close to 4.2V.
* We then check the brownout status. If the brownout status is false,
* the voltage is already close to the target voltage of 4.2V so we
* can go ahead and set the 4P2 current limit to our max target limit.
* If the brownout status is true, we need to ramp us the current limit
* so that we don't cause large inrush current issues. We step up the
* current limit until the brownout status is false or until we've
* reached our maximum defined 4p2 current limit.
*/
clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
POWER_DCDC4P2_BO_MASK,
22 << POWER_DCDC4P2_BO_OFFSET); /* 4.15V */
if (!(readl(&power_regs->hw_power_sts) & POWER_STS_DCDC_4P2_BO)) {
setbits_le32(&power_regs->hw_power_5vctrl,
0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
} else {
tmp = (readl(&power_regs->hw_power_5vctrl) &
POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK) >>
POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
while (tmp < 0x3f) {
if (!(readl(&power_regs->hw_power_sts) &
POWER_STS_DCDC_4P2_BO)) {
tmp = readl(&power_regs->hw_power_5vctrl);
tmp |= POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
early_delay(100);
writel(tmp, &power_regs->hw_power_5vctrl);
break;
} else {
tmp++;
tmp2 = readl(&power_regs->hw_power_5vctrl);
tmp2 &= ~POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
tmp2 |= tmp <<
POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
writel(tmp2, &power_regs->hw_power_5vctrl);
early_delay(100);
}
}
}
clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK);
writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
}
/*-----------------------------------------------------------------------------+
* denali_core_search_data_eye.
+----------------------------------------------------------------------------*/
void denali_core_search_data_eye(unsigned long memory_size)
{
int k, j;
u32 val;
u32 wr_dqs_shift, dqs_out_shift, dll_dqs_delay_X;
u32 max_passing_cases = 0, wr_dqs_shift_with_max_passing_cases = 0;
u32 passing_cases = 0, dll_dqs_delay_X_sw_val = 0;
u32 dll_dqs_delay_X_start_window = 0, dll_dqs_delay_X_end_window = 0;
volatile u32 *ram_pointer;
u32 test[NUM_TRIES] = {
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
ram_pointer = (volatile u32 *)(CFG_SDRAM_BASE);
for (wr_dqs_shift = 64; wr_dqs_shift < 96; wr_dqs_shift++) {
/*for (wr_dqs_shift=1; wr_dqs_shift<96; wr_dqs_shift++) {*/
/* -----------------------------------------------------------+
* De-assert 'start' parameter.
* ----------------------------------------------------------*/
mtdcr(ddrcfga, DDR0_02);
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
mtdcr(ddrcfgd, val);
/* -----------------------------------------------------------+
* Set 'wr_dqs_shift'
* ----------------------------------------------------------*/
mtdcr(ddrcfga, DDR0_09);
val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK)
| DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift);
mtdcr(ddrcfgd, val);
/* -----------------------------------------------------------+
* Set 'dqs_out_shift' = wr_dqs_shift + 32
* ----------------------------------------------------------*/
dqs_out_shift = wr_dqs_shift + 32;
mtdcr(ddrcfga, DDR0_22);
val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK)
| DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift);
mtdcr(ddrcfgd, val);
passing_cases = 0;
for (dll_dqs_delay_X = 1; dll_dqs_delay_X < 64; dll_dqs_delay_X++) {
/*for (dll_dqs_delay_X=1; dll_dqs_delay_X<128; dll_dqs_delay_X++) {*/
/* -----------------------------------------------------------+
* Set 'dll_dqs_delay_X'.
* ----------------------------------------------------------*/
/* dll_dqs_delay_0 */
mtdcr(ddrcfga, DDR0_17);
val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK)
| DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X);
mtdcr(ddrcfgd, val);
/* dll_dqs_delay_1 to dll_dqs_delay_4 */
mtdcr(ddrcfga, DDR0_18);
val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK)
| DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X)
| DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X)
| DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X)
| DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X);
mtdcr(ddrcfgd, val);
/* dll_dqs_delay_5 to dll_dqs_delay_8 */
mtdcr(ddrcfga, DDR0_19);
val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK)
| DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X)
| DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X)
| DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X)
| DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X);
mtdcr(ddrcfgd, val);
ppcMsync();
ppcMbar();
/* -----------------------------------------------------------+
* Assert 'start' parameter.
* ----------------------------------------------------------*/
mtdcr(ddrcfga, DDR0_02);
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON;
mtdcr(ddrcfgd, val);
ppcMsync();
ppcMbar();
/* -----------------------------------------------------------+
* Wait for the DCC master delay line to finish calibration
* ----------------------------------------------------------*/
if (wait_for_dlllock() != 0) {
printf("dlllock did not occur !!!\n");
printf("denali_core_search_data_eye!!!\n");
printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n",
wr_dqs_shift, dll_dqs_delay_X);
hang();
}
ppcMsync();
ppcMbar();
if (wait_for_dram_init_complete() != 0) {
printf("dram init complete did not occur !!!\n");
printf("denali_core_search_data_eye!!!\n");
printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n",
wr_dqs_shift, dll_dqs_delay_X);
hang();
}
udelay(100); /* wait 100us to ensure init is really completed !!! */
/* write values */
for (j=0; j<NUM_TRIES; j++) {
ram_pointer[j] = test[j];
/* clear any cache at ram location */
__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
}
/* read values back */
for (j=0; j<NUM_TRIES; j++) {
for (k=0; k<NUM_READS; k++) {
/* clear any cache at ram location */
__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
if (ram_pointer[j] != test[j])
break;
}
/* read error */
if (k != NUM_READS)
break;
}
/* See if the dll_dqs_delay_X value passed.*/
if (j < NUM_TRIES) {
/* Failed */
passing_cases = 0;
/* break; */
} else {
/* Passed */
if (passing_cases == 0)
dll_dqs_delay_X_sw_val = dll_dqs_delay_X;
passing_cases++;
if (passing_cases >= max_passing_cases) {
max_passing_cases = passing_cases;
wr_dqs_shift_with_max_passing_cases = wr_dqs_shift;
dll_dqs_delay_X_start_window = dll_dqs_delay_X_sw_val;
dll_dqs_delay_X_end_window = dll_dqs_delay_X;
}
}
/* -----------------------------------------------------------+
* De-assert 'start' parameter.
* ----------------------------------------------------------*/
mtdcr(ddrcfga, DDR0_02);
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
mtdcr(ddrcfgd, val);
} /* for (dll_dqs_delay_X=0; dll_dqs_delay_X<128; dll_dqs_delay_X++) */
} /* for (wr_dqs_shift=0; wr_dqs_shift<96; wr_dqs_shift++) */
/* -----------------------------------------------------------+
* Largest passing window is now detected.
* ----------------------------------------------------------*/
/* Compute dll_dqs_delay_X value */
dll_dqs_delay_X = (dll_dqs_delay_X_end_window + dll_dqs_delay_X_start_window) / 2;
wr_dqs_shift = wr_dqs_shift_with_max_passing_cases;
debug("DQS calibration - Window detected:\n");
debug("max_passing_cases = %d\n", max_passing_cases);
debug("wr_dqs_shift = %d\n", wr_dqs_shift);
debug("dll_dqs_delay_X = %d\n", dll_dqs_delay_X);
debug("dll_dqs_delay_X window = %d - %d\n",
dll_dqs_delay_X_start_window, dll_dqs_delay_X_end_window);
/* -----------------------------------------------------------+
* De-assert 'start' parameter.
* ----------------------------------------------------------*/
mtdcr(ddrcfga, DDR0_02);
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
mtdcr(ddrcfgd, val);
/* -----------------------------------------------------------+
* Set 'wr_dqs_shift'
* ----------------------------------------------------------*/
mtdcr(ddrcfga, DDR0_09);
val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK)
| DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift);
mtdcr(ddrcfgd, val);
debug("DDR0_09=0x%08lx\n", val);
/* -----------------------------------------------------------+
* Set 'dqs_out_shift' = wr_dqs_shift + 32
* ----------------------------------------------------------*/
dqs_out_shift = wr_dqs_shift + 32;
mtdcr(ddrcfga, DDR0_22);
val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK)
| DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift);
mtdcr(ddrcfgd, val);
debug("DDR0_22=0x%08lx\n", val);
/* -----------------------------------------------------------+
* Set 'dll_dqs_delay_X'.
* ----------------------------------------------------------*/
/* dll_dqs_delay_0 */
mtdcr(ddrcfga, DDR0_17);
val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK)
| DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X);
mtdcr(ddrcfgd, val);
debug("DDR0_17=0x%08lx\n", val);
/* dll_dqs_delay_1 to dll_dqs_delay_4 */
mtdcr(ddrcfga, DDR0_18);
val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK)
| DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X)
| DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X)
| DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X)
| DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X);
mtdcr(ddrcfgd, val);
debug("DDR0_18=0x%08lx\n", val);
/* dll_dqs_delay_5 to dll_dqs_delay_8 */
mtdcr(ddrcfga, DDR0_19);
val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK)
| DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X)
| DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X)
| DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X)
| DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X);
mtdcr(ddrcfgd, val);
debug("DDR0_19=0x%08lx\n", val);
/* -----------------------------------------------------------+
* Assert 'start' parameter.
* ----------------------------------------------------------*/
mtdcr(ddrcfga, DDR0_02);
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON;
mtdcr(ddrcfgd, val);
ppcMsync();
ppcMbar();
/* -----------------------------------------------------------+
* Wait for the DCC master delay line to finish calibration
* ----------------------------------------------------------*/
if (wait_for_dlllock() != 0) {
printf("dlllock did not occur !!!\n");
hang();
}
ppcMsync();
ppcMbar();
if (wait_for_dram_init_complete() != 0) {
printf("dram init complete did not occur !!!\n");
hang();
}
udelay(100); /* wait 100us to ensure init is really completed !!! */
}
void main() {
allegrosetup(scrwid,scrhei);
makepalette(&greypalette);
mypalette(255,0,0,0);
mypalette(0,0,0,0);
mypalette(255,1,1,1);
mypalette(128,0,0,0);
for (int r=0;r<8;r++) {
for (int g=0;g<8;g++) {
int palc=r+g*8;
mypalette(palc,(r==0?0:0.1+0.6*r/7.0),(g==0?0:0.1+0.2*g/7.0),(g==0?0:0.1+0.7*g/7.0));
// Good colours: mypalette(palc,(r==0?0:0.3+0.4*r/7.0),(g==0?0:0.1+0.2*g/7.0),(g==0?0:0.3+0.5*g/7.0));
}
}
randomise();
V3d pos=V3d(0,0,0);
V3d vel=V3d(0,0,0);
V3d acc=V3d(0,0,0);
Ori ori;
float droll=0;
float dyaw=0;
float roll=0;
float yaw=0;
float pitch=0;
int frame=0;
List<V3d> particles=List<V3d>(gridsize*gridsize*gridsize);
for (int i=1;i<gridsize*gridsize*gridsize;i++) {
particles+gridsize*V3d(floatrnd(-1,1),floatrnd(-1,1),floatrnd(-1,1));
}
starttimer();
do {
frame++;
float pd=1.6+1.3*sin(2*pi*frame/1000.0);
PPsetup(scrwid,scrhei,pd);
left.clear(0);
right.clear(0);
// b.fadeby(16);
V3d off=V3d(mymod(pos.x,gridsize),mymod(pos.y,gridsize),mymod(pos.z,gridsize));
int ioff=-mydiv(pos.x,gjump);
int joff=-mydiv(pos.y,gjump);
int koff=-mydiv(pos.z,gjump);
ori.quickorisetup();
// Need to find largest axis, and do loops with that one outside
int ks=mysgn(ori.qz.z);
int js=-mysgn(ori.qz.y);
int is=-mysgn(ori.qz.x);
for (int i=1;i<=particles.len;i++) {
int x,y;
V3d p=particles.num(i);
//V3d cen=p-off;
V3d cen=p+pos;
cen=V3d(mymod2(cen.x,-gridsize,gridsize),mymod2(cen.y,-gridsize,gridsize),mymod2(cen.z,-gridsize,gridsize));
cen=V3d::qorientate(cen,ori);
int c=7.0-chop(6.0*(cen.z+gridsize)/(float)(gridsize*2),0,6);
plotsphere(cen,c);
}
for (int i=0;i<scrwid;i++) {
for (int j=0;j<scrhei;j++) {
b.bmp[j][i]=(left.bmp[j][i] | right.bmp[j][i]);
}
}
b.writetoscreen();
acc=hang(acc,V3d::origin,0.95,0.01);
vel=hang(vel,(ori.qz/5.0).neg(),0.9,0)+acc;
pos=pos+vel;
droll=hang(droll,0,0.9,0.01);
dyaw=hang(dyaw,0,0.95,0.01);
roll=hang(roll,0,0.95,0)+droll;
yaw=hang(yaw,0,0.92,0)+dyaw;
pitch=hang(pitch,0,0.999,0.01);
pos=pos+ori.qz*4;
ori.roll(roll/5.0);
ori.yaw(yaw/5.0);
pos=pos-ori.z()*4;
framedone();
} while (!key[KEY_SPACE] && !key[KEY_ESC]);
savetimer();
allegro_exit();
displayframespersecond();
}
void imx_esdctlv4_do_write_delay_line_calibration(void)
{
void __iomem *base = IOMEM(MX53_ESDCTL_BASE_ADDR);
void __iomem *adr;
u32 val;
/*
* configure ESCTL to normal operation so we can
* write the compare values
*/
writel(ESDCTL_V4_ESDSCR_CMD_NOP, base + ESDCTL_V4_ESDSCR);
/* write test-pattern to RAM */
/* ESCTL uses this address for calibration */
adr = IOMEM(MX53_CSD0_BASE_ADDR) + 0x10000000;
writel(0, adr + 0x00);
writel(0, adr + 0x0c);
writel(0, adr + 0x10);
writel(0, adr + 0x1c);
writel(0, adr + 0x20);
writel(0, adr + 0x2c);
writel(0, adr + 0x30);
writel(0, adr + 0x4c);
writel(0xffffffff, adr + 0x04);
writel(0xffffffff, adr + 0x08);
writel(0xffffffff, adr + 0x14);
writel(0xffffffff, adr + 0x18);
writel(0xffffffff, adr + 0x24);
writel(0xffffffff, adr + 0x28);
writel(0xffffffff, adr + 0x34);
writel(0xffffffff, adr + 0x48);
/* pre-charge all RAM banks */
val = ESDCTL_V4_ESDSCR_CON_REQ | ESDCTL_V4_ESDSCR_CMD_CS0 |
ESDCTL_V4_ESDSCR_CMD_PRE_ALL;
writel(val, base + ESDCTL_V4_ESDSCR);
val = ESDCTL_V4_ESDSCR_CON_REQ | ESDCTL_V4_ESDSCR_CMD_CS1 |
ESDCTL_V4_ESDSCR_CMD_PRE_ALL;
writel(val, base + ESDCTL_V4_ESDSCR);
/* write test-pattern to ESCTL */
writel(0x00ffff00, base + ESDCTL_V4_PDCMPR1);
writel(0, base + ESDCTL_V4_PDCMPR2);
/* start write delay-line calibration */
writel(ESDCTL_V4_WRDLHWCTL_HW_WDL_EN, base + ESDCTL_V4_WRDLHWCTL);
do {
val = readl(base + ESDCTL_V4_WRDLHWCTL);
} while (val & ESDCTL_V4_WRDLHWCTL_HW_WDL_EN);
val &= ESDCTL_V4_WRDLHWCTL_HW_WDL_ERR3 |
ESDCTL_V4_WRDLHWCTL_HW_WDL_ERR2 |
ESDCTL_V4_WRDLHWCTL_HW_WDL_ERR1 |
ESDCTL_V4_WRDLHWCTL_HW_WDL_ERR0;
if (val)
hang();
}
void board_init_r(gd_t *dummy1, ulong dummy2)
{
int i;
debug(">>spl:board_init_r()\n");
#if defined(CONFIG_SYS_SPL_MALLOC_START)
mem_malloc_init(CONFIG_SYS_SPL_MALLOC_START,
CONFIG_SYS_SPL_MALLOC_SIZE);
gd->flags |= GD_FLG_FULL_MALLOC_INIT;
#endif
if (!(gd->flags & GD_FLG_SPL_INIT)) {
if (spl_init())
hang();
}
#ifndef CONFIG_PPC
/*
* timer_init() does not exist on PPC systems. The timer is initialized
* and enabled (decrementer) in interrupt_init() here.
*/
timer_init();
#endif
#ifdef CONFIG_SPL_BOARD_INIT
spl_board_init();
#endif
board_boot_order(spl_boot_list);
for (i = 0; i < ARRAY_SIZE(spl_boot_list) &&
spl_boot_list[i] != BOOT_DEVICE_NONE; i++) {
announce_boot_device(spl_boot_list[i]);
if (!spl_load_image(spl_boot_list[i]))
break;
}
if (i == ARRAY_SIZE(spl_boot_list) ||
spl_boot_list[i] == BOOT_DEVICE_NONE) {
puts("SPL: failed to boot from all boot devices\n");
hang();
}
switch (spl_image.os) {
case IH_OS_U_BOOT:
debug("Jumping to U-Boot\n");
break;
#ifdef CONFIG_SPL_OS_BOOT
case IH_OS_LINUX:
debug("Jumping to Linux\n");
spl_board_prepare_for_linux();
jump_to_image_linux((void *)CONFIG_SYS_SPL_ARGS_ADDR);
#endif
default:
debug("Unsupported OS image.. Jumping nevertheless..\n");
}
#if defined(CONFIG_SYS_MALLOC_F_LEN) && !defined(CONFIG_SYS_SPL_MALLOC_SIZE)
debug("SPL malloc() used %#lx bytes (%ld KB)\n", gd->malloc_ptr,
gd->malloc_ptr / 1024);
#endif
debug("loaded - jumping to U-Boot...");
spl_board_prepare_for_boot();
jump_to_image_no_args(&spl_image);
}
static void ddr_phy_param_init(unsigned int mode)
{
int i;
unsigned int timeout = 10000;
ddr_writel(DDRP_DCR_VALUE, DDRP_DCR);
ddr_writel(DDRP_MR0_VALUE, DDRP_MR0);
ddr_writel(DDRP_MR3_VALUE, DDRP_MR3);
#ifdef CONFIG_SYS_DDR_CHIP_ODT
ddr_writel(0, DDRP_ODTCR);
#endif
ddr_writel(DDRP_PTR0_VALUE, DDRP_PTR0);
ddr_writel(DDRP_PTR1_VALUE, DDRP_PTR1);
ddr_writel(DDRP_PTR2_VALUE, DDRP_PTR2);
ddr_writel(DDRP_DTPR0_VALUE, DDRP_DTPR0);
ddr_writel(DDRP_DTPR1_VALUE, DDRP_DTPR1);
ddr_writel(DDRP_DTPR2_VALUE, DDRP_DTPR2);
// for (i = 0; i < 4; i++) {
// unsigned int tmp = ddr_readl(DDRP_DXGCR(i));
//
// tmp &= ~(3 << 9);
//#ifdef CONFIG_DDR_PHY_ODT
//#ifdef CONFIG_DDR_PHY_DQ_ODT
// tmp |= 1 << 10;
//#endif /* CONFIG_DDR_PHY_DQ_ODT */
//#ifdef CONFIG_DDR_PHY_DQS_ODT
// tmp |= 1 << 9;
//#endif /* CONFIG_DDR_PHY_DQS_ODT */
//#endif /* CONFIG_DDR_PHY_ODT */
//#ifndef CONFIG_DDR_HOST_CC
// if ((i > 1) && (ddr_params_p->dw32 == 0))
// tmp &= ~DDRP_DXGCR_DXEN;
//#elif (CONFIG_DDR_DW32 == 0)
// if (i > 1)
// tmp &= ~DDRP_DXGCR_DXEN;
//#endif /* CONFIG_DDR_HOST_CC */
// ddr_writel(tmp, DDRP_DXGCR(i));
// }
ddr_writel(DDRP_PGCR_VALUE, DDRP_PGCR);
/***************************************************************
* DXCCR:
* DQSRES: 4...7bit is DQSRES[].
* DQSNRES: 8...11bit is DQSRES[] too.
*
* Selects the on-die pull-down/pull-up resistor for DQS pins.
* DQSRES[3]: selects pull-down (when set to 0) or pull-up (when set to 1).
* DQSRES[2:0] selects the resistor value as follows:
* 000 = Open: On-die resistor disconnected
* 001 = 688 ohms
* 010 = 611 ohms
* 011 = 550 ohms
* 100 = 500 ohms
* 101 = 458 ohms
* 110 = 393 ohms
* 111 = 344 ohms
*****************************************************************
* Note: DQS resistor must be connected for LPDDR/LPDDR2 *
*****************************************************************
* the config will affect power and stablity
*/
ddr_writel(0x30c00813, DDRP_ACIOCR);
ddr_writel(0x4802, DDRP_DXCCR);
while (!(ddr_readl(DDRP_PGSR) == (DDRP_PGSR_IDONE
| DDRP_PGSR_DLDONE
| DDRP_PGSR_ZCDONE))
&& (ddr_readl(DDRP_PGSR) != 0x1f)
&& --timeout);
if (timeout == 0) {
printf("DDR PHY init timeout: PGSR=%X\n", ddr_readl(DDRP_PGSR));
hang();
}
}
/*
* early system init of muxing and clocks.
*/
void s_init(void)
{
__maybe_unused struct am335x_baseboard_id header;
#ifdef CONFIG_NOR_BOOT
asm("stmfd sp!, {r2 - r4}");
asm("movw r4, #0x8A4");
asm("movw r3, #0x44E1");
asm("orr r4, r4, r3, lsl #16");
asm("mov r2, #9");
asm("mov r3, #8");
asm("gpmc_mux: str r2, [r4], #4");
asm("subs r3, r3, #1");
asm("bne gpmc_mux");
asm("ldmfd sp!, {r2 - r4}");
#endif
/* WDT1 is already running when the bootloader gets control
* Disable it to avoid "random" resets
*/
writel(0xAAAA, &wdtimer->wdtwspr);
while (readl(&wdtimer->wdtwwps) != 0x0)
;
writel(0x5555, &wdtimer->wdtwspr);
while (readl(&wdtimer->wdtwwps) != 0x0)
;
#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
/* Setup the PLLs and the clocks for the peripherals */
pll_init();
/* Enable RTC32K clock */
rtc32k_enable();
/* UART softreset */
u32 regVal;
enable_uart0_pin_mux();
regVal = readl(&uart_base->uartsyscfg);
regVal |= UART_RESET;
writel(regVal, &uart_base->uartsyscfg);
while ((readl(&uart_base->uartsyssts) &
UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
;
/* Disable smart idle */
regVal = readl(&uart_base->uartsyscfg);
regVal |= UART_SMART_IDLE_EN;
writel(regVal, &uart_base->uartsyscfg);
#if defined(CONFIG_NOR_BOOT)
/* NOR booting - enable serial console */
gd = (gd_t *) ((CONFIG_SYS_INIT_SP_ADDR) & ~0x07);
gd->baudrate = CONFIG_BAUDRATE;
serial_init();
gd->have_console = 1;
#else
gd = &gdata;
preloader_console_init();
#endif
/* Initalize the board header */
enable_i2c0_pin_mux();
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#ifndef CONFIG_NOR_BOOT
if (read_eeprom() < 0)
puts("Could not get board ID.\n");
#endif
/* Check if baseboard eeprom is available */
if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
puts("Could not probe the EEPROM; something fundamentally "
"wrong on the I2C bus.\n");
}
/* read the eeprom using i2c */
if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header,
sizeof(header))) {
puts("Could not read the EEPROM; something fundamentally"
" wrong on the I2C bus.\n");
}
if (header.magic != 0xEE3355AA) {
/*
* read the eeprom using i2c again,
* but use only a 1 byte address
*/
if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1,
(uchar *)&header, sizeof(header))) {
puts("Could not read the EEPROM; something "
"fundamentally wrong on the I2C bus.\n");
hang();
}
if (header.magic != 0xEE3355AA) {
printf("Incorrect magic number (0x%x) in EEPROM\n",
header.magic);
hang();
}
}
enable_board_pin_mux(&header);
if (!strncmp("A335X_SK", header.name, HDR_NAME_LEN)) {
/*
* EVM SK 1.2A and later use gpio0_7 to enable DDR3.
* This is safe enough to do on older revs.
*/
gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
gpio_direction_output(GPIO_DDR_VTT_EN, 1);
}
#ifdef CONFIG_NOR_BOOT
am33xx_spl_board_init();
#endif
/* The following boards are known to use DDR3. */
if ((!strncmp("A335X_SK", header.name, HDR_NAME_LEN)) ||
(!strncmp("A33515BB", header.name, 8) &&
strncmp("1.5", header.version, 3) <= 0))
config_ddr(EMIF_REG_SDRAM_TYPE_DDR3);
else
config_ddr(EMIF_REG_SDRAM_TYPE_DDR2);
#endif
}
void start_armboot (void)
{
init_fnc_t **init_fnc_ptr;
int i;
uchar *buf;
for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
if ((*init_fnc_ptr)() != 0) {
hang ();
}
}
misc_init_r();
buf = (uchar*) CFG_LOADADDR;
/* Always first try mmc without checking boot pins */
#ifndef CONFIG_OMAP3_BEAGLE
if ((get_mem_type() == MMC_ONENAND) || (get_mem_type() == MMC_NAND))
#endif /* CONFIG_OMAP3_BEAGLE */
buf += mmc_boot(buf);
if (buf == (uchar *)CFG_LOADADDR) {
if (get_mem_type() == GPMC_NAND){
#ifdef CFG_PRINTF
printf("Booting from nand . . .\n");
#endif
for (i = NAND_UBOOT_START; i < NAND_UBOOT_END; i+= NAND_BLOCK_SIZE){
if (!nand_read_block(buf, i))
buf += NAND_BLOCK_SIZE; /* advance buf ptr */
}
}
if (get_mem_type() == GPMC_ONENAND){
#ifdef CFG_PRINTF
printf("Booting from onenand . . .\n");
#endif
for (i = ONENAND_START_BLOCK; i < ONENAND_END_BLOCK; i++){
if (!onenand_read_block(buf, i))
buf += ONENAND_BLOCK_SIZE;
}
}
}
#if defined (CONFIG_AM3517EVM)
/*
* FIXME: Currently coping uboot image,
* ideally we should leverage XIP feature here
*/
if (get_mem_type() == GPMC_NOR) {
int size;
printf("Booting from NOR Flash...\n");
size = nor_read_boot(buf);
if (size > 0)
buf += size;
}
#endif
if (buf == (uchar *)CFG_LOADADDR)
hang();
/* go run U-Boot and never return */
printf("Starting OS Bootloader...\n");
((init_fnc_t *)CFG_LOADADDR)();
/* should never come here */
}
void main() {
allegrosetup(scrwid,scrhei);
makepalette(&greypalette);
mypalette(255,0,0,0);
mypalette(0,0,0,0);
mypalette(255,1,1,1);
mypalette(128,0,0,0);
randomise();
for (int i=0;i<=15;i++) {
waves+Wave();
// waves.num(i).display();
}
for (int r=0;r<16;r++) {
for (int g=0;g<16;g++) {
int palc=r+g*16;
mypalette(palc,(r==0?0:brightness+0.2+change*0.5*r/15.0),(g==0?0:brightness+change*0.1+0.2*g/15.0),(g==0?0:brightness+change*0.2+0.6*g/15.0));
// Groovy colours mypalette(palc,(r==0?0:0.1+0.6*r/15.0),(g==0?0:0.1+0.2*g/15.0),(g==0?0:0.1+0.7*g/15.0));
// Good colours: mypalette(palc,(r==0?0:0.3+0.4*r/15.0),(g==0?0:0.1+0.2*g/15.0),(g==0?0:0.3+0.5*g/15.0));
}
}
V3d vel=V3d(0,0,0);
V3d acc=V3d(0,0,0);
Ori ori;
float droll=0;
float dyaw=0;
float dpitch=0;
int frame=0;
List<V3d> particles=List<V3d>(gridsize*gridsize*gridsize);
/* for (int i=1;i<gridsize*gridsize*gridsize;i++) {
particles+gridsize*V3d(floatrnd(-1,1),floatrnd(-1,1),floatrnd(-1,1));
}*/
int ps=1;
float rad=0;
for (float thru=0;thru<1.0;thru+=0.0016) {
V3d here=getpos(thru);
V3d forward=getpos(thru+0.00001)-here;
V3d up=V3d::normcross(V3d::crazy,forward);
V3d right=V3d::normcross(forward,up);
for (int i=0;i<ps;i++) {
float t=2*pi*(float)i/(float)ps;
float s=sin(t);
float c=cos(t);
particles+(here+rad*(s*up+c*right));
}
// v.print();
}
starttimer();
float thru=0;
float marker=0;
V3d pos=getpos(marker);
V3d *tail=new V3d[taillen];
int tailpos=0;
do {
thru+=0.001;
// V3d last=V3d(pos.x,pos.y,pos.z);
// V3d pos=getpos(thru);
// V3d next=getpos(thru+0.00001);
// V3d newz=next-pos;
// ori.forcez(newz);
frame++;
// float pd=1.6+1.3*sin(2*pi*frame/1000.0);
float pd=2.0;
PPsetup(scrwid,scrhei,pd);
left.clear(0);
right.clear(0);
// b.fadeby(16);
int ioff=-mydiv(pos.x,gjump);
int joff=-mydiv(pos.y,gjump);
int koff=-mydiv(pos.z,gjump);
ori.quickorisetup();
// Need to find largest axis, and do loops with that one outside
int ks=mysgn(ori.qz.z);
int js=-mysgn(ori.qz.y);
int is=-mysgn(ori.qz.x);
for (int i=1;i<=particles.len;i++) {
int x,y;
V3d p=particles.num(i);
V3d cen=p-pos+0.0*ori.y;
cen=V3d::disorientate(cen,ori);
int c=15.0-chop(14.0*(cen.z+gridsize)/(float)(gridsize*2),0,14);
// int c=7.0-chop(6.0*(i/particles.len),0,6);
plotsphere(cen,c);
}
// Plot and move marker
V3d m;
for (int i=1;i<=15;i++) {
m=V3d::disorientate(getpos(marker)-pos,ori);
if (m.mod()<markerrange)
marker+=0.0002;
}
float u=PPgetunitnoadd(m);
bool plot=false;
if (u) {
int x,y;
float rad=0.08*u;
PPgetscrposnoadd(m,PPlefteye,&x,&y);
if (left.inimage(x,y)) {
plot=true;
left.opencircle(x,y,rad,15);
}
PPgetscrposnoadd(m,PPrighteye,&x,&y);
if (right.inimage(x,y)) {
plot=true;
right.opencircle(x,y,rad,15*16);
}
}
if (!plot) {
V2d v=scrwid*2*V2d(m.x,m.y).norm();
if (abs(v.x)>scrwid/2) {
float change=(float)scrwid/2.0/abs(v.x);
v=change*v;
}
if (abs(v.y)>scrhei/2) {
float change=(float)scrhei/2.0/abs(v.y);
v=change*v;
}
v=v+V2d(scrwid/2,scrhei/2);
left.opencircle(v,5,15);
right.opencircle(v,5,15*16);
}
// Pull player towards marker
// if (m.mod()>markerrange+.1) {
V3d pulldir=getpos(marker)-pos;
// vel=vel+pulldir*0.02;
// float amount=(V3d::normdot(ori.z(),pulldir)+5.0)/6.0;
float amount=chop(0.99-(m.mod()-markerrange)/5.0,0,1);
V3d newz=ori.z()*amount+(1.0-amount)*pulldir;
ori.forcez(newz);
// vel=vel*amount;
//
//}
// Draw and update tail
V3d last=(tail[tailpos]-pos).disorientate(ori);
for (int k=1;k<taillen;k++) {
int j=mymod(tailpos+k,taillen);
V3d next=(tail[j]-pos).disorientate(ori);
plotline(last,next,(float)k/(float)taillen);
last=next;
}
if ((frame % 5)==0) {
tail[tailpos]=pos-ori.qz;
tailpos=mymod(tailpos+1,taillen);
}
// Or screens
for (int i=0;i<scrwid;i++) {
for (int j=0;j<scrhei;j++) {
b.bmp[j][i]=(left.bmp[j][i] | right.bmp[j][i]);
}
}
b.writetoscreen();
// acc=hang(acc,V3d::origin,0.95,0.01);
// Movement
float angvel=turnability;
if (key[KEY_LCONTROL])
vel=vel+ori.z()*forcevel;
else
angvel=turnability*2.0;
if (key[KEY_UP])
dpitch=dpitch+angvel;
if (key[KEY_DOWN])
dpitch=dpitch-angvel;
if (key[KEY_LEFT])
if (key[KEY_ALT])
droll=droll-angvel;
else
dyaw=dyaw-angvel;
if (key[KEY_RIGHT])
if (key[KEY_ALT])
droll=droll+angvel;
else
dyaw=dyaw+angvel;
vel=hang(vel,V3d::o,0.91,0);
pos=pos+vel;
droll=hang(droll,0,0.9,0);
dyaw=hang(dyaw,0,0.9,0);
dpitch=hang(dpitch,0,0.9,0);
ori.roll(droll/5.0);
ori.yaw(dyaw/5.0);
ori.pitch(dpitch/5.0);
framedone();
} while (!key[KEY_SPACE] && !key[KEY_ESC]);
savetimer();
allegro_exit();
displayframespersecond();
}
void board_init_r(gd_t *id, ulong dest_addr)
{
ulong malloc_start;
#if !defined(CONFIG_SYS_NO_FLASH)
ulong flash_size;
#endif
gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_R, "board_init_r");
monitor_flash_len = _end_ofs;
/* Enable caches */
enable_caches();
debug("monitor flash len: %08lX\n", monitor_flash_len);
board_init(); /* Setup chipselects */
/*
* TODO: printing of the clock inforamtion of the board is now
* implemented as part of bdinfo command. Currently only support for
* davinci SOC's is added. Remove this check once all the board
* implement this.
*/
#ifdef CONFIG_CLOCKS
set_cpu_clk_info(); /* Setup clock information */
#endif
serial_initialize();
debug("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
#ifdef CONFIG_LOGBUFFER
logbuff_init_ptrs();
#endif
#ifdef CONFIG_POST
post_output_backlog();
#endif
/* The Malloc area is immediately below the monitor copy in DRAM */
malloc_start = dest_addr - TOTAL_MALLOC_LEN;
mem_malloc_init (malloc_start, TOTAL_MALLOC_LEN);
#ifdef CONFIG_ARCH_EARLY_INIT_R
arch_early_init_r();
#endif
power_init_board();
#if !defined(CONFIG_SYS_NO_FLASH)
puts("Flash: ");
flash_size = flash_init();
if (flash_size > 0) {
# ifdef CONFIG_SYS_FLASH_CHECKSUM
print_size(flash_size, "");
/*
* Compute and print flash CRC if flashchecksum is set to 'y'
*
* NOTE: Maybe we should add some WATCHDOG_RESET()? XXX
*/
if (getenv_yesno("flashchecksum") == 1) {
printf(" CRC: %08X", crc32(0,
(const unsigned char *) CONFIG_SYS_FLASH_BASE,
flash_size));
}
putc('\n');
# else /* !CONFIG_SYS_FLASH_CHECKSUM */
print_size(flash_size, "\n");
# endif /* CONFIG_SYS_FLASH_CHECKSUM */
} else {
puts(failed);
hang();
}
#endif
#if defined(CONFIG_CMD_NAND)
puts("NAND: ");
nand_init(); /* go init the NAND */
#endif
#if defined(CONFIG_CMD_ONENAND)
onenand_init();
#endif
#ifdef CONFIG_GENERIC_MMC
puts("MMC: ");
mmc_initialize(gd->bd);
#endif
#ifdef CONFIG_HAS_DATAFLASH
AT91F_DataflashInit();
dataflash_print_info();
#endif
/* initialize environment */
if (should_load_env())
env_relocate();
else
set_default_env(NULL);
#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
arm_pci_init();
#endif
stdio_init(); /* get the devices list going. */
jumptable_init();
#if defined(CONFIG_API)
/* Initialize API */
api_init();
#endif
console_init_r(); /* fully init console as a device */
#ifdef CONFIG_DISPLAY_BOARDINFO_LATE
# ifdef CONFIG_OF_CONTROL
/* Put this here so it appears on the LCD, now it is ready */
display_fdt_model(gd->fdt_blob);
# else
checkboard();
# endif
#endif
#if defined(CONFIG_ARCH_MISC_INIT)
/* miscellaneous arch dependent initialisations */
arch_misc_init();
#endif
#if defined(CONFIG_MISC_INIT_R)
/* miscellaneous platform dependent initialisations */
misc_init_r();
#endif
/* set up exceptions */
interrupt_init();
/* enable exceptions */
enable_interrupts();
#ifndef CONFIG_ROCKCHIP
/* Initialize from environment */
load_addr = getenv_ulong("loadaddr", 16, load_addr);
#endif
#ifdef CONFIG_BOARD_LATE_INIT
board_late_init();
#endif
#ifdef CONFIG_BITBANGMII
bb_miiphy_init();
#endif
#if defined(CONFIG_CMD_NET)
puts("Net: ");
eth_initialize(gd->bd);
#if defined(CONFIG_RESET_PHY_R)
debug("Reset Ethernet PHY\n");
reset_phy();
#endif
#endif
#ifdef CONFIG_POST
post_run(NULL, POST_RAM | post_bootmode_get(0));
#endif
#if defined(CONFIG_PRAM) || defined(CONFIG_LOGBUFFER)
/*
* Export available size of memory for Linux,
* taking into account the protected RAM at top of memory
*/
{
ulong pram = 0;
uchar memsz[32];
#ifdef CONFIG_PRAM
pram = getenv_ulong("pram", 10, CONFIG_PRAM);
#endif
#ifdef CONFIG_LOGBUFFER
#ifndef CONFIG_ALT_LB_ADDR
/* Also take the logbuffer into account (pram is in kB) */
pram += (LOGBUFF_LEN + LOGBUFF_OVERHEAD) / 1024;
#endif
#endif
sprintf((char *)memsz, "%ldk", (gd->ram_size / 1024) - pram);
setenv("mem", (char *)memsz);
}
#endif
/* main_loop() can return to retry autoboot, if so just run it again. */
for (;;) {
main_loop();
}
/* NOTREACHED - no way out of command loop except booting */
}
void panic(const char* msg) {
terminal_printf("KERNEL PANIC: %s", msg);
interrupts_disable();
hang();
};
void board_init_f(ulong bootflag)
{
bd_t *bd;
init_fnc_t **init_fnc_ptr;
int j;
#ifndef CONFIG_SYS_NO_FLASH
ulong flash_size;
#endif
gd = (gd_t *) (CONFIG_SYS_GBL_DATA_OFFSET);
/* Clear initial global data */
memset((void *)gd, 0, sizeof(gd_t));
gd->bd = (bd_t *) (gd + 1); /* At end of global data */
gd->baudrate = CONFIG_BAUDRATE;
gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
bd = gd->bd;
bd->bi_memstart = CONFIG_SYS_RAM_BASE;
bd->bi_memsize = CONFIG_SYS_RAM_SIZE;
bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
#if defined(CONFIG_SYS_SRAM_BASE) && defined(CONFIG_SYS_SRAM_SIZE)
bd->bi_sramstart = CONFIG_SYS_SRAM_BASE;
bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE;
#endif
bd->bi_baudrate = CONFIG_BAUDRATE;
bd->bi_bootflags = bootflag; /* boot / reboot flag (for LynxOS) */
gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
gd->reloc_off = CONFIG_SYS_RELOC_MONITOR_BASE - CONFIG_SYS_MONITOR_BASE;
for (init_fnc_ptr = init_sequence, j = 0; *init_fnc_ptr;
++init_fnc_ptr, j++) {
#ifdef DEBUG_INIT_SEQUENCE
if (j > 9)
str_init_seq[9] = '0' + (j / 10);
str_init_seq[10] = '0' + (j - (j / 10) * 10);
serial_puts(str_init_seq);
#endif
if ((*init_fnc_ptr + gd->reloc_off) () != 0) {
hang();
}
}
#ifdef DEBUG_INIT_SEQUENCE
serial_puts(str_init_seq_done);
#endif
/*
* Now that we have DRAM mapped and working, we can
* relocate the code and continue running from DRAM.
*
* Reserve memory at end of RAM for (top down in that order):
* - kernel log buffer
* - protected RAM
* - LCD framebuffer
* - monitor code
* - board info struct
*/
#ifdef DEBUG_MEM_LAYOUT
printf("CONFIG_SYS_MONITOR_BASE: 0x%lx\n", CONFIG_SYS_MONITOR_BASE);
printf("CONFIG_ENV_ADDR: 0x%lx\n", CONFIG_ENV_ADDR);
printf("CONFIG_SYS_RELOC_MONITOR_BASE: 0x%lx (%d)\n", CONFIG_SYS_RELOC_MONITOR_BASE,
CONFIG_SYS_MONITOR_LEN);
printf("CONFIG_SYS_MALLOC_BASE: 0x%lx (%d)\n", CONFIG_SYS_MALLOC_BASE,
CONFIG_SYS_MALLOC_LEN);
printf("CONFIG_SYS_INIT_SP_OFFSET: 0x%lx (%d)\n", CONFIG_SYS_INIT_SP_OFFSET,
CONFIG_SYS_STACK_SIZE);
printf("CONFIG_SYS_PROM_OFFSET: 0x%lx (%d)\n", CONFIG_SYS_PROM_OFFSET,
CONFIG_SYS_PROM_SIZE);
printf("CONFIG_SYS_GBL_DATA_OFFSET: 0x%lx (%d)\n", CONFIG_SYS_GBL_DATA_OFFSET,
GENERATED_GBL_DATA_SIZE);
#endif
#ifdef CONFIG_POST
post_bootmode_init();
post_run(NULL, POST_ROM | post_bootmode_get(0));
#endif
#if defined(CONFIG_NEEDS_MANUAL_RELOC)
/*
* We have to relocate the command table manually
*/
fixup_cmdtable(ll_entry_start(cmd_tbl_t, cmd),
ll_entry_count(cmd_tbl_t, cmd));
#endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */
#if defined(CONFIG_CMD_AMBAPP) && defined(CONFIG_SYS_AMBAPP_PRINT_ON_STARTUP)
puts("AMBA:\n");
do_ambapp_print(NULL, 0, 0, NULL);
#endif
/* initialize higher level parts of CPU like time base and timers */
cpu_init_r();
/* start timer */
timer_interrupt_init();
/*
* Enable Interrupts before any calls to udelay,
* the flash driver may use udelay resulting in
* a hang if not timer0 IRQ is enabled.
*/
interrupt_init();
/* The Malloc area is immediately below the monitor copy in RAM */
mem_malloc_init(CONFIG_SYS_MALLOC_BASE,
CONFIG_SYS_MALLOC_END - CONFIG_SYS_MALLOC_BASE);
#if !defined(CONFIG_SYS_NO_FLASH)
puts("Flash: ");
if ((flash_size = flash_init()) > 0) {
# ifdef CONFIG_SYS_FLASH_CHECKSUM
print_size(flash_size, "");
/*
* Compute and print flash CRC if flashchecksum is set to 'y'
*
* NOTE: Maybe we should add some WATCHDOG_RESET()? XXX
*/
if (getenv_yesno("flashchecksum") == 1) {
printf(" CRC: %08lX",
crc32(0, (const unsigned char *)CONFIG_SYS_FLASH_BASE,
flash_size)
);
}
putc('\n');
# else /* !CONFIG_SYS_FLASH_CHECKSUM */
print_size(flash_size, "\n");
# endif /* CONFIG_SYS_FLASH_CHECKSUM */
} else {
puts(failed);
hang();
}
bd->bi_flashstart = CONFIG_SYS_FLASH_BASE; /* update start of FLASH memory */
bd->bi_flashsize = flash_size; /* size of FLASH memory (final value) */
#if CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE
bd->bi_flashoffset = monitor_flash_len; /* reserved area for startup monitor */
#else
bd->bi_flashoffset = 0;
#endif
#else /* CONFIG_SYS_NO_FLASH */
bd->bi_flashsize = 0;
bd->bi_flashstart = 0;
bd->bi_flashoffset = 0;
#endif /* !CONFIG_SYS_NO_FLASH */
#ifdef CONFIG_SPI
# if !defined(CONFIG_ENV_IS_IN_EEPROM)
spi_init_f();
# endif
spi_init_r();
#endif
/* relocate environment function pointers etc. */
env_relocate();
#if defined(CONFIG_BOARD_LATE_INIT)
board_late_init();
#endif
#ifdef CONFIG_ID_EEPROM
mac_read_from_eeprom();
#endif
#if defined(CONFIG_PCI)
/*
* Do pci configuration
*/
pci_init();
#endif
/* Initialize stdio devices */
stdio_init();
/* Initialize the jump table for applications */
jumptable_init();
/* Initialize the console (after the relocation and devices init) */
console_init_r();
#ifdef CONFIG_STATUS_LED
status_led_set(STATUS_LED_BOOT, STATUS_LED_BLINKING);
#endif
udelay(20);
/* Initialize from environment */
load_addr = getenv_ulong("loadaddr", 16, load_addr);
WATCHDOG_RESET();
#if defined(CONFIG_CMD_DOC)
WATCHDOG_RESET();
puts("DOC: ");
doc_init();
#endif
#ifdef CONFIG_BITBANGMII
bb_miiphy_init();
#endif
#if defined(CONFIG_CMD_NET)
WATCHDOG_RESET();
puts("Net: ");
eth_initialize(bd);
#endif
#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
WATCHDOG_RESET();
debug("Reset Ethernet PHY\n");
reset_phy();
#endif
#ifdef CONFIG_POST
post_run(NULL, POST_RAM | post_bootmode_get(0));
#endif
#if defined(CONFIG_CMD_IDE)
WATCHDOG_RESET();
puts("IDE: ");
ide_init();
#endif /* CONFIG_CMD_IDE */
#ifdef CONFIG_LAST_STAGE_INIT
WATCHDOG_RESET();
/*
* Some parts can be only initialized if all others (like
* Interrupts) are up and running (i.e. the PC-style ISA
* keyboard).
*/
last_stage_init();
#endif
#ifdef CONFIG_PS2KBD
puts("PS/2: ");
kbd_init();
#endif
prom_init();
/* main_loop */
for (;;) {
WATCHDOG_RESET();
main_loop();
}
}
void sh_generic_init(void)
{
DECLARE_GLOBAL_DATA_PTR;
bd_t *bd;
init_fnc_t **init_fnc_ptr;
memset(gd, 0, CONFIG_SYS_GBL_DATA_SIZE);
gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
gd->bd = (bd_t *)(gd + 1); /* At end of global data */
gd->baudrate = CONFIG_BAUDRATE;
gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
bd = gd->bd;
bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
#if defined(CONFIG_SYS_SRAM_BASE) && defined(CONFIG_SYS_SRAM_SIZE)
bd->bi_sramstart = CONFIG_SYS_SRAM_BASE;
bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE;
#endif
bd->bi_baudrate = CONFIG_BAUDRATE;
for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
WATCHDOG_RESET();
if ((*init_fnc_ptr) () != 0)
hang();
}
#ifdef CONFIG_WATCHDOG
/* disable watchdog if environment is set */
{
char *s = getenv("watchdog");
if (s != NULL)
if (strncmp(s, "off", 3) == 0)
WATCHDOG_DISABLE();
}
#endif /* CONFIG_WATCHDOG*/
#ifdef CONFIG_BITBANGMII
bb_miiphy_init();
#endif
#if defined(CONFIG_CMD_NET)
{
char *s;
puts("Net: ");
eth_initialize(gd->bd);
s = getenv("bootfile");
if (s != NULL)
copy_filename(BootFile, s, sizeof(BootFile));
}
#endif /* CONFIG_CMD_NET */
while (1) {
WATCHDOG_RESET();
main_loop();
}
}
void start_armboot (void)
{
init_fnc_t **init_fnc_ptr;
char *s;
#if defined(CONFIG_VFD) || defined(CONFIG_LCD)
unsigned long addr;
#endif
/* Pointer is writable since we allocated a register for it */
gd = (gd_t*)(_armboot_start - CONFIG_SYS_MALLOC_LEN - sizeof(gd_t));
/* compiler optimization barrier needed for GCC >= 3.4 */
__asm__ __volatile__("": : :"memory");
memset ((void*)gd, 0, sizeof (gd_t));
gd->bd = (bd_t*)((char*)gd - sizeof(bd_t));
memset (gd->bd, 0, sizeof (bd_t));
gd->flags |= GD_FLG_RELOC;
monitor_flash_len = _bss_start - _armboot_start;
for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
if ((*init_fnc_ptr)() != 0) {
hang ();
}
}
/* armboot_start is defined in the board-specific linker script */
mem_malloc_init (_armboot_start - CONFIG_SYS_MALLOC_LEN,
CONFIG_SYS_MALLOC_LEN);
#ifndef CONFIG_SYS_NO_FLASH
/* configure available FLASH banks */
display_flash_config (flash_init ());
#endif /* CONFIG_SYS_NO_FLASH */
#ifdef CONFIG_VFD
# ifndef PAGE_SIZE
# define PAGE_SIZE 4096
# endif
/*
* reserve memory for VFD display (always full pages)
*/
/* bss_end is defined in the board-specific linker script */
addr = (_bss_end + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
vfd_setmem (addr);
gd->fb_base = addr;
#endif /* CONFIG_VFD */
#ifdef CONFIG_LCD
/* board init may have inited fb_base */
if (!gd->fb_base) {
# ifndef PAGE_SIZE
# define PAGE_SIZE 4096
# endif
/*
* reserve memory for LCD display (always full pages)
*/
/* bss_end is defined in the board-specific linker script */
addr = (_bss_end + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
lcd_setmem (addr);
gd->fb_base = addr;
}
#endif /* CONFIG_LCD */
#if defined(CONFIG_CMD_NAND)
puts ("NAND: ");
nand_init(); /* go init the NAND */
#endif
#if defined(CONFIG_CMD_ONENAND)
onenand_init();
#endif
#ifdef CONFIG_HAS_DATAFLASH
AT91F_DataflashInit();
dataflash_print_info();
#endif
#if defined(CONFIG_CMD_SF)
spi_flash_probe(0, 0, 0, 0);
#endif
#ifdef CONFIG_GENERIC_MMC
puts("MMC: ");
mmc_initialize(gd->bd);
mmc_flash_init();
#endif
/* initialize environment */
env_relocate ();
#ifdef CONFIG_VFD
/* must do this after the framebuffer is allocated */
drv_vfd_init();
#endif /* CONFIG_VFD */
#ifdef CONFIG_SERIAL_MULTI
serial_initialize();
#endif
/* IP Address */
gd->bd->bi_ip_addr = getenv_IPaddr ("ipaddr");
stdio_init (); /* get the devices list going. */
jumptable_init ();
#if defined(CONFIG_API)
/* Initialize API */
api_init ();
#endif
console_init_r (); /* fully init console as a device */
#if defined(CONFIG_ARCH_MISC_INIT)
/* miscellaneous arch dependent initialisations */
arch_misc_init ();
#endif
#if defined(CONFIG_MISC_INIT_R)
/* miscellaneous platform dependent initialisations */
misc_init_r ();
#endif
/* enable exceptions */
enable_interrupts ();
/* Perform network card initialisation if necessary */
#ifdef CONFIG_DRIVER_TI_EMAC
/* XXX: this needs to be moved to board init */
extern void davinci_eth_set_mac_addr (const u_int8_t *addr);
if (getenv ("ethaddr")) {
uchar enetaddr[6];
eth_getenv_enetaddr("ethaddr", enetaddr);
davinci_eth_set_mac_addr(enetaddr);
}
#endif
#if defined(CONFIG_DRIVER_SMC91111) || defined (CONFIG_DRIVER_LAN91C96)
/* XXX: this needs to be moved to board init */
if (getenv ("ethaddr")) {
uchar enetaddr[6];
eth_getenv_enetaddr("ethaddr", enetaddr);
smc_set_mac_addr(enetaddr);
}
#endif /* CONFIG_DRIVER_SMC91111 || CONFIG_DRIVER_LAN91C96 */
/* Initialize from environment */
if ((s = getenv ("loadaddr")) != NULL) {
load_addr = simple_strtoul (s, NULL, 16);
}
#if defined(CONFIG_CMD_NET)
if ((s = getenv ("bootfile")) != NULL) {
copy_filename (BootFile, s, sizeof (BootFile));
}
#endif
#ifdef BOARD_LATE_INIT
board_late_init ();
#endif
#ifdef CONFIG_BITBANGMII
bb_miiphy_init();
#endif
#if defined(CONFIG_CMD_NET)
#if defined(CONFIG_NET_MULTI)
puts ("Net: ");
#endif
eth_initialize(gd->bd);
#if defined(CONFIG_RESET_PHY_R)
debug ("Reset Ethernet PHY\n");
reset_phy();
#endif
#endif
#if defined(CONFIG_BOOTROM_SUPPORT)
extern void download_boot(const int (*handle)(void));
download_boot(NULL);
#endif
product_control();
/* main_loop() can return to retry autoboot, if so just run it again. */
for (;;) {
main_loop ();
}
/* NOTREACHED - no way out of command loop except booting */
}
int switch_boot_mode(void)
{
unsigned long hold_time = 50000, polling_time = 10000, tmp;
unsigned long upgrade_step;
upgrade_step = simple_strtoul (getenv ("upgrade_step"), NULL, 16);
printf("upgrade_step = %d !!!!!!!!!!!!!!!!!!\n", upgrade_step);
saradc_enable();
#ifdef CONFIG_UBI_SUPPORT
powerkey_hold(0);
run_command ("ubi part system", 0);
powerkey_hold(0);
run_command ("ubifsmount system", 0);
//run_command ("ubifsls", 0);
#endif
powerkey_led_off();
if(upgrade_step == 3)
{
switch(reboot_mode)
{
case AMLOGIC_NORMAL_BOOT:
{
printf("AMLOGIC_NORMAL_BOOT...\n");
power_hold();
//green led on red led off
powerkey_led_on();
SET_MPEG_REG_MASK(VPP_MISC, VPP_POST_FG_OSD2 | VPP_PRE_FG_OSD2);
logo_display();
return 1;
}
case AMLOGIC_FACTORY_RESET_REBOOT:
{
printf("AMLOGIC_FACTORY_RESET_REBOOT...\n");
power_hold();
//green led on red led off
powerkey_led_on();
SET_MPEG_REG_MASK(VPP_MISC, VPP_POST_FG_OSD2 | VPP_PRE_FG_OSD2);
logo_display();
run_command ("nand read ${recovery_name} ${loadaddr} 0 ${recovery_size}", 0);
run_command ("bootm", 0);
break;
}
case AMLOGIC_UPDATE_REBOOT:
{
printf("AMLOGIC_UPDATE_REBOOT...\n");
power_hold();
//green led on red led off
powerkey_led_on();
SET_MPEG_REG_MASK(VPP_MISC, VPP_POST_FG_OSD2 | VPP_PRE_FG_OSD2);
logo_display();
run_command ("set upgrade_step 0", 0);
run_command ("save", 0);
upgrade_step = 0;
break;
}
case AMLOGIC_CHARGING_REBOOT:
{
printf("AMLOGIC_POWERDOWN... \n");
if(is_ac_connected)
{
power_unhold();
hang();
}
}
default:
{
printf("Default.... \n");
if(is_ac_connected)
{
power_hold();
#ifdef CONFIG_BATTERY_CHARGING
battery_charging();
#endif
}
else
{
powerkey_hold(0);
if(get_powerkey_hold_count())
{
#ifdef CONFIG_BATTERY_CHARGING
if(get_battery_percentage() < 10)
{
power_low_display();
sdelay(2);
power_unhold();
printf("Low Power!!!\nPower Down!\n");
hang();
}
#endif
power_hold();
printf("Power Up!\n");
}
else
{
power_unhold();
printf("Power Down!\n");
hang();
}
}
//green led on red led off
powerkey_led_on();
SET_MPEG_REG_MASK(VPP_MISC, VPP_POST_FG_OSD2 | VPP_PRE_FG_OSD2);
logo_display();
break;
}
}
}
else
{
power_hold();
powerkey_led_on();
SET_MPEG_REG_MASK(VPP_MISC, VPP_POST_FG_OSD2 | VPP_PRE_FG_OSD2);
logo_display();
printf("Upgrade step %d...\n", upgrade_step);
}
if(upgrade_step == 0)
{
if(upgrade_bootloader())
{
run_command ("set upgrade_step 1", 0);
run_command ("save", 0);
run_command ("reset", 0);
hang();
}
else
{
printf("### ERROR: u-boot write failed!!!\n");
return -1;
}
}
else if((upgrade_step >0) && (upgrade_step < 3))
{
if(upgrade_step == 1)
{
if(upgrade_env())
{
run_command ("set upgrade_step 2", 0);
run_command ("save", 0);
run_command ("reset", 0);
hang();
}
else
{
run_command ("defenv", 0);
run_command ("save", 0);
}
}
run_command ("set upgrade_step 3", 0);
run_command ("save", 0);
//upgrade_partition();
into_recovery();
}
//added by Elvis for added fool idle
get_key();
get_key();
while(hold_time > 0)
{
udelay(polling_time);
tmp = get_key();
printf("get_key(): %d\n", tmp);
if(!tmp) break;
hold_time -= polling_time;
}
if(hold_time > 0)
{
aml_autoscript();
printf("Normal Start...\n");
return 1;
}
else
{
if(upgrade_bootloader())
{
run_command ("set upgrade_step 1", 0);
run_command ("save", 0);
run_command ("reset", 0);
hang();
}
if(upgrade_env())
{
run_command ("set upgrade_step 2", 0);
run_command ("save", 0);
run_command ("reset", 0);
hang();
}
run_command ("set upgrade_step 3", 0);
run_command ("save", 0);
#ifndef CONFIG_UBI_SUPPORT
//upgrade_partition();
#endif
into_recovery();
}
}
static bool isr0(__UNUSED registers_t regs){
console_printErr("Division by zero exception raised!\n");
asm volatile("int $1");
hang();
return false;
}
void board_init (void)
{
bd_t *bd;
init_fnc_t **init_fnc_ptr;
static gd_t gd_data;
static bd_t bd_data;
/* Pointer is writable since we allocated a register for it. */
gd = &gd_data;
/* compiler optimization barrier needed for GCC >= 3.4 */
__asm__ __volatile__("": : :"memory");
gd->bd = &bd_data;
gd->baudrate = CONFIG_BAUDRATE;
gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
bd = gd->bd;
bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
#ifndef CONFIG_SYS_NO_FLASH
bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
#endif
#if defined(CONFIG_SYS_SRAM_BASE) && defined(CONFIG_SYS_SRAM_SIZE)
bd->bi_sramstart= CONFIG_SYS_SRAM_BASE;
bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE;
#endif
bd->bi_baudrate = CONFIG_BAUDRATE;
for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
WATCHDOG_RESET ();
if ((*init_fnc_ptr) () != 0) {
hang ();
}
}
WATCHDOG_RESET ();
/* The Malloc area is immediately below the monitor copy in RAM */
mem_malloc_init(CONFIG_SYS_MALLOC_BASE, CONFIG_SYS_MALLOC_LEN);
#ifndef CONFIG_SYS_NO_FLASH
WATCHDOG_RESET ();
bd->bi_flashsize = flash_init();
#endif
#ifdef CONFIG_CMD_NAND
puts("NAND: ");
nand_init();
#endif
#ifdef CONFIG_GENERIC_MMC
puts("MMC: ");
mmc_initialize(bd);
#endif
WATCHDOG_RESET ();
env_relocate();
WATCHDOG_RESET ();
stdio_init();
jumptable_init();
console_init_r();
WATCHDOG_RESET ();
interrupt_init ();
#if defined(CONFIG_BOARD_LATE_INIT)
board_late_init ();
#endif
#if defined(CONFIG_CMD_NET)
puts ("Net: ");
eth_initialize (bd);
#endif
/* main_loop */
for (;;) {
WATCHDOG_RESET ();
main_loop ();
}
}