void
platform_init_ap(int cpuid)
{
unsigned ciu_int_mask, clock_int_mask, ipi_int_mask;
/*
* Set the exception base.
*/
mips_wr_ebase(0x80000000);
/*
* Clear any pending IPIs.
*/
cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cpuid), 0xffffffff);
/*
* Set up interrupts.
*/
octeon_ciu_reset();
/*
* Unmask the clock, ipi and ciu interrupts.
*/
ciu_int_mask = hard_int_mask(0);
clock_int_mask = hard_int_mask(5);
ipi_int_mask = hard_int_mask(platform_ipi_intrnum());
set_intr_mask(ciu_int_mask | clock_int_mask | ipi_int_mask);
mips_wbflush();
}
void
platform_init_ap(int cpuid)
{
int ipi_int_mask, clock_int_mask;
/*
* Unmask the clock and ipi interrupts.
*/
clock_int_mask = hard_int_mask(5);
ipi_int_mask = hard_int_mask(platform_ipi_intrnum());
set_intr_mask(ipi_int_mask | clock_int_mask);
}
void
platform_init_ap(int cpuid)
{
uint32_t status;
register_t hwrena;
u_int clock_int_mask;
KASSERT(cpuid < MAXCPU, ("%s: invalid CPU id %d", __func__, cpuid));
/* Make sure coprocessors are enabled. */
status = mips_rd_status();
status |= (MIPS_SR_COP_0_BIT | MIPS_SR_COP_1_BIT);
#if defined(CPU_CHERI)
status |= MIPS_SR_COP_2_BIT;
#endif
mips_wr_status(status);
/* Enable HDWRD instruction in userspace. */
hwrena = mips_rd_hwrena();
hwrena |= (MIPS_HWRENA_CC | MIPS_HWRENA_CCRES | MIPS_HWRENA_CPUNUM);
mips_wr_hwrena(hwrena);
/*
* Enable per-thread timer.
*/
clock_int_mask = hard_int_mask(5);
set_intr_mask(clock_int_mask);
}
void
platform_init_ap(int cpuid)
{
int ipi_int_mask, clock_int_mask;
KASSERT(cpuid == 1, ("AP has an invalid cpu id %d", cpuid));
/*
* Make sure that kseg0 is mapped cacheable-coherent
*/
kseg0_map_coherent();
sb_intr_init(cpuid);
/*
* Unmask the clock and ipi interrupts.
*/
clock_int_mask = hard_int_mask(5);
ipi_int_mask = hard_int_mask(platform_ipi_intrnum());
set_intr_mask(ipi_int_mask | clock_int_mask);
}
void
platform_init_ap(int cpuid)
{
unsigned reg;
/*
* Clear any pending IPIs.
*/
mips_wr_xburst_core_sts(~(JZ_CORESTS_MIRQ0P << cpuid));
/* Allow IPI mbox for this core */
reg = mips_rd_xburst_reim();
reg |= (JZ_REIM_MIRQ0M << cpuid);
mips_wr_xburst_reim(reg);
/*
* Unmask the ipi interrupts.
*/
reg = hard_int_mask(platform_ipi_hardintr_num());
set_intr_mask(reg);
}
