int nios_legacy_vctcxo_trim_dac_write(struct bladerf *dev, uint16_t value)
{
int status;
struct uart_cmd cmd;
int base;
/* FPGA v0.0.4 introduced a change to the location of the DAC registers */
const bool legacy_location = !have_cap(dev, BLADERF_CAP_UPDATED_DAC_ADDR);
base = legacy_location ? 0 : 34;
cmd.addr = base;
cmd.data = value & 0xff;
status = nios_access(dev,
legacy_location ?
NIOS_PKT_LEGACY_DEV_VCTCXO :
NIOS_PKT_LEGACY_DEV_CONFIG,
USB_DIR_HOST_TO_DEVICE, &cmd, 1);
if (status < 0) {
return status;
}
cmd.addr = base + 1;
cmd.data = (value >> 8) & 0xff;
status = nios_access(dev,
legacy_location ?
NIOS_PKT_LEGACY_DEV_VCTCXO :
NIOS_PKT_LEGACY_DEV_CONFIG,
USB_DIR_HOST_TO_DEVICE, &cmd, 1);
return status;
}
static bool fpga_supports_tuning_mode(struct bladerf *dev,
bladerf_tuning_mode mode)
{
switch (mode) {
case BLADERF_TUNING_MODE_HOST:
return true;
case BLADERF_TUNING_MODE_FPGA:
return have_cap(dev, BLADERF_CAP_FPGA_TUNING);
default:
return false;
}
}
