int hdmirx_wr_phy(uint8_t reg_address, uint16_t data)
{
int error = 0;
int cnt = 0;
//hdmirx_wr_dwc(RA_I2CM_PHYG3_SLAVE, 0x39);
hdmirx_wr_dwc(RA_I2CM_PHYG3_ADDRESS, reg_address);
hdmirx_wr_dwc(RA_I2CM_PHYG3_DATAO, data);
hdmirx_wr_dwc(RA_I2CM_PHYG3_OPERATION, 0x01); /* write op */
do{ //wait i2cmpdone
if(hdmirx_rd_dwc(RA_HDMI_ISTS)&(1<<28)){
hdmirx_wr_dwc(RA_HDMI_ICLR, 1<<28);
break;
}
cnt++;
if(cnt>10000){
printk("[HDMIRX error]: %s(%x,%x,%x) timeout\n", __func__, 0x39, reg_address, data);
break;
}
}while(1);
if(hdmirx_log_flag & 0x2){
printk("Write PHY Reg 0x%08x <= 0x%08x\n", reg_address, data);
}
return error;
}
void hdmirx_hw_reset(void)
{
hdmirx_print("%s %d\n", __func__, rx.port);
//WRITE_CBUS_REG(RESET0_REGISTER, 0x8); //reset HDMIRX module
//mdelay(10);
//clk_init();
hdmirx_wr_top(HDMIRX_TOP_INTR_MASKN, 0); //disable top interrupt gate
hdmirx_wr_top( HDMIRX_TOP_SW_RESET, 0x3f);
mdelay(1);
control_reset(0);
hdmirx_wr_top( HDMIRX_TOP_PORT_SEL, (1<<rx.port)); //EDID port select
hdmirx_interrupts_cfg(false); //disable dwc interrupt
if(hdcp_enable){
hdmi_rx_ctrl_hdcp_config(&rx.hdcp);
} else {
hdmirx_wr_bits_dwc( RA_HDCP_CTRL, HDCP_ENABLE, 0);
}
/*phy config*/
//hdmirx_phy_restart();
//hdmi_rx_phy_fast_switching(1);
phy_init(rx.port, 0); //port, dcm
/**/
/* control config */
control_init(rx.port);
audio_init();
packet_init();
hdmirx_audio_fifo_rst();
hdmirx_packet_fifo_rst();
/**/
control_reset(1);
/*enable irq */
hdmirx_wr_top(HDMIRX_TOP_INTR_STAT_CLR, ~0);
hdmirx_wr_top(HDMIRX_TOP_INTR_MASKN, 0x00001fff);
hdmirx_interrupts_hpd(true);
/**/
#ifndef USE_GPIO_FOR_HPD
hdmi_rx_ctrl_hpd(true);
hdmirx_wr_top( HDMIRX_TOP_HPD_PWR5V, (1<<5)|(1<<4)); //invert HDP output
#endif
/* wait at least 4 video frames (at 24Hz) : 167ms for the mode detection
recover the video mode */
mdelay(200);
/* Check If HDCP engine is in Idle state, if not wait for authentication time.
200ms is enough if no Ri errors */
if (hdmirx_rd_dwc(0xe0) != 0)
{
mdelay(200);
}
}
uint16_t hdmirx_rd_phy(uint8_t reg_address)
{
int cnt = 0;
//hdmirx_wr_dwc(RA_I2CM_PHYG3_SLAVE, 0x39);
hdmirx_wr_dwc(RA_I2CM_PHYG3_ADDRESS, reg_address);
hdmirx_wr_dwc(RA_I2CM_PHYG3_OPERATION, 0x02); /* read op */
do{ //wait i2cmpdone
if(hdmirx_rd_dwc(RA_HDMI_ISTS)&(1<<28)){
hdmirx_wr_dwc(RA_HDMI_ICLR, 1<<28);
break;
}
cnt++;
if(cnt>10000){
printk("[HDMIRX error]: %s(%x,%x) timeout\n", __func__, 0x39, reg_address);
break;
}
}while(1);
return (uint16_t)(hdmirx_rd_dwc(RA_I2CM_PHYG3_DATAI));
}
void hdmirx_audio_enable(bool en)
{
unsigned int val = hdmirx_rd_dwc(RA_AUD_SAO_CTRL);
if (en) {
if (val != 1)
hdmirx_wr_dwc(RA_AUD_SAO_CTRL, 1);
} else {
if (val != 0x7ff)
hdmirx_wr_dwc(RA_AUD_SAO_CTRL, 0x7ff);
}
}
void hdmirx_read_audio_info(struct aud_info_s* audio_info)
{
/*get AudioInfo */
audio_info->coding_type = hdmirx_rd_bits_dwc(RA_PDEC_AIF_PB0, CODING_TYPE);
audio_info->channel_count = hdmirx_rd_bits_dwc(RA_PDEC_AIF_PB0, CHANNEL_COUNT);
audio_info->sample_frequency = hdmirx_rd_bits_dwc(RA_PDEC_AIF_PB0, SAMPLE_FREQ);
audio_info->sample_size = hdmirx_rd_bits_dwc(RA_PDEC_AIF_PB0, SAMPLE_SIZE);
audio_info->coding_extension = hdmirx_rd_bits_dwc(RA_PDEC_AIF_PB0, AIF_DATA_BYTE_3);
audio_info->channel_allocation = hdmirx_rd_bits_dwc(RA_PDEC_AIF_PB0, CH_SPEAK_ALLOC);
audio_info->down_mix_inhibit = hdmirx_rd_bits_dwc(RA_PDEC_AIF_PB1, DWNMIX_INHIBIT);
audio_info->level_shift_value = hdmirx_rd_bits_dwc(RA_PDEC_AIF_PB1, LEVEL_SHIFT_VAL);
audio_info->cts = hdmirx_rd_dwc(RA_PDEC_ACR_CTS);
audio_info->n = hdmirx_rd_dwc(RA_PDEC_ACR_N);
if(audio_info->cts!=0){
audio_info->audio_recovery_clock = (hdmirx_get_tmds_clock()/audio_info->cts)
*audio_info->n/128;
}
else{
audio_info->audio_recovery_clock = 0;
}
}
void hdmirx_wr_bits_dwc( uint16_t addr, uint32_t mask, uint32_t value)
{
hdmirx_wr_dwc(addr, set(hdmirx_rd_dwc(addr), mask, value));
}
uint32_t hdmirx_rd_bits_dwc( uint16_t addr, uint32_t mask)
{
return get(hdmirx_rd_dwc(addr), mask);
}
int hdmirx_get_pdec_aud_sts(void)
{
return (hdmirx_rd_dwc(RA_PDEC_AUD_STS));
}