static void hdmi_rx_ctrl_hdcp_config( const struct hdmi_rx_ctrl_hdcp *hdcp)
{
int error = 0;
unsigned i = 0;
unsigned k = 0;
hdmirx_wr_bits_dwc( RA_HDCP_CTRL, HDCP_ENABLE, 0);
//hdmirx_wr_bits_dwc(ctx, RA_HDCP_CTRL, KEY_DECRYPT_ENABLE, 1);
hdmirx_wr_bits_dwc( RA_HDCP_CTRL, KEY_DECRYPT_ENABLE, 0);
hdmirx_wr_dwc(RA_HDCP_SEED, hdcp->seed);
for (i = 0; i < HDCP_KEYS_SIZE; i += 2) {
for (k = 0; k < HDCP_KEY_WR_TRIES; k++) {
if (hdmirx_rd_bits_dwc( RA_HDCP_STS, HDCP_KEY_WR_OK_STS) != 0) {
break;
}
}
if (k < HDCP_KEY_WR_TRIES) {
hdmirx_wr_dwc(RA_HDCP_KEY1, hdcp->keys[i + 0]);
hdmirx_wr_dwc(RA_HDCP_KEY0, hdcp->keys[i + 1]);
} else {
error = -EAGAIN;
break;
}
}
hdmirx_wr_dwc(RA_HDCP_BKSV1, hdcp->bksv[0]);
hdmirx_wr_dwc(RA_HDCP_BKSV0, hdcp->bksv[1]);
hdmirx_wr_bits_dwc( RA_HDCP_RPT_CTRL, REPEATER, hdcp->repeat? 1 : 0);
hdmirx_wr_dwc(RA_HDCP_RPT_BSTATUS, 0); /* nothing attached downstream */
hdmirx_wr_bits_dwc( RA_HDCP_CTRL, HDCP_ENABLE, 1);
}
void hdmirx_phy_hw_reset(void)
{
hdmirx_wr_bits_dwc(RA_SNPS_PHYG3_CTRL, MSK(2,0), 0x3);
mdelay(1);
hdmirx_wr_bits_dwc(RA_SNPS_PHYG3_CTRL, MSK(2,0), 0x2);
mdelay(1);
hdmirx_wr_bits_dwc(RA_SNPS_PHYG3_CTRL, MSK(2,0), 0x0);
}
int hdmirx_packet_fifo_rst(void)
{
int error = 0;
hdmirx_wr_bits_dwc(RA_PDEC_CTRL, PD_FIFO_FILL_INFO_CLR|PD_FIFO_CLR, ~0);
hdmirx_wr_bits_dwc(RA_PDEC_CTRL, PD_FIFO_FILL_INFO_CLR|PD_FIFO_CLR, 0);
return error;
}
int hdmirx_audio_fifo_rst(void)
{
int error = 0;
hdmirx_wr_bits_dwc(RA_AUD_FIFO_CTRL, AFIF_INIT, 1);
hdmirx_wr_bits_dwc(RA_AUD_FIFO_CTRL, AFIF_INIT, 0);
return error;
}
int hdmirx_control_clk_range(unsigned long min, unsigned long max)
{
int error = 0;
unsigned evaltime = 0;
unsigned long ref_clk;
ref_clk = rx.ctrl.md_clk;
evaltime = (ref_clk * 4095) / 158000;
min = (min * evaltime) / ref_clk;
max = (max * evaltime) / ref_clk;
hdmirx_wr_bits_dwc(RA_HDMI_CKM_F, MINFREQ, min);
hdmirx_wr_bits_dwc(RA_HDMI_CKM_F, CKM_MAXFREQ, max);
return error;
}
static int control_init(unsigned port)
{
int err = 0;
unsigned evaltime = 0;
evaltime = (rx.ctrl.md_clk * 4095) / 158000;
hdmirx_wr_dwc(RA_HDMI_OVR_CTRL, ~0); /* enable all */
hdmirx_wr_bits_dwc(RA_HDMI_SYNC_CTRL, VS_POL_ADJ_MODE, VS_POL_ADJ_AUTO);
hdmirx_wr_bits_dwc(RA_HDMI_SYNC_CTRL, HS_POL_ADJ_MODE, HS_POL_ADJ_AUTO);
hdmirx_wr_bits_dwc(RA_HDMI_CKM_EVLTM, EVAL_TIME, evaltime);
hdmirx_control_clk_range(TMDS_CLK_MIN, TMDS_CLK_MAX);
/* bit field shared between phy and controller */
hdmirx_wr_bits_dwc(RA_HDMI_PCB_CTRL, INPUT_SELECT, port);
hdmirx_wr_bits_dwc(RA_SNPS_PHYG3_CTRL, ((1 << 2) - 1) << 2, port);
control_init_more();
return err;
}
void hdmirx_hw_reset(void)
{
hdmirx_print("%s %d\n", __func__, rx.port);
//WRITE_CBUS_REG(RESET0_REGISTER, 0x8); //reset HDMIRX module
//mdelay(10);
//clk_init();
hdmirx_wr_top(HDMIRX_TOP_INTR_MASKN, 0); //disable top interrupt gate
hdmirx_wr_top( HDMIRX_TOP_SW_RESET, 0x3f);
mdelay(1);
control_reset(0);
hdmirx_wr_top( HDMIRX_TOP_PORT_SEL, (1<<rx.port)); //EDID port select
hdmirx_interrupts_cfg(false); //disable dwc interrupt
if(hdcp_enable){
hdmi_rx_ctrl_hdcp_config(&rx.hdcp);
} else {
hdmirx_wr_bits_dwc( RA_HDCP_CTRL, HDCP_ENABLE, 0);
}
/*phy config*/
//hdmirx_phy_restart();
//hdmi_rx_phy_fast_switching(1);
phy_init(rx.port, 0); //port, dcm
/**/
/* control config */
control_init(rx.port);
audio_init();
packet_init();
hdmirx_audio_fifo_rst();
hdmirx_packet_fifo_rst();
/**/
control_reset(1);
/*enable irq */
hdmirx_wr_top(HDMIRX_TOP_INTR_STAT_CLR, ~0);
hdmirx_wr_top(HDMIRX_TOP_INTR_MASKN, 0x00001fff);
hdmirx_interrupts_hpd(true);
/**/
#ifndef USE_GPIO_FOR_HPD
hdmi_rx_ctrl_hpd(true);
hdmirx_wr_top( HDMIRX_TOP_HPD_PWR5V, (1<<5)|(1<<4)); //invert HDP output
#endif
/* wait at least 4 video frames (at 24Hz) : 167ms for the mode detection
recover the video mode */
mdelay(200);
/* Check If HDCP engine is in Idle state, if not wait for authentication time.
200ms is enough if no Ri errors */
if (hdmirx_rd_dwc(0xe0) != 0)
{
mdelay(200);
}
}
static void hdmi_rx_ctrl_hpd(bool enable)
{
hdmirx_wr_bits_dwc(RA_HDMI_SETUP_CTRL, HOT_PLUG_DETECT, enable? 1 : 0);
}
void hdmirx_phy_pddq(int enable)
{
hdmirx_wr_bits_dwc(RA_SNPS_PHYG3_CTRL, MSK(1,1), enable);
}
void hdmirx_phy_reset(bool enable)
{
hdmirx_wr_bits_dwc(RA_SNPS_PHYG3_CTRL, MSK(1,0), enable);
}
static void phy_wrapper_svsretmode(int enable)
{
hdmirx_wr_bits_dwc(RA_SNPS_PHYG3_CTRL, MSK(1,6), enable);
}
//#define PHY_GEN3_GLUE_I2C_SLAVE_ADDR (0x48UL)
static void phy_set_cfgclk_freq(int cfgclk)
{
hdmirx_wr_bits_dwc(RA_SNPS_PHYG3_CTRL, MSK(2,4), cfgclk);
}
