int hdmirx_wr_phy(uint8_t reg_address, uint16_t data)
{
int error = 0;
int cnt = 0;
//hdmirx_wr_dwc(RA_I2CM_PHYG3_SLAVE, 0x39);
hdmirx_wr_dwc(RA_I2CM_PHYG3_ADDRESS, reg_address);
hdmirx_wr_dwc(RA_I2CM_PHYG3_DATAO, data);
hdmirx_wr_dwc(RA_I2CM_PHYG3_OPERATION, 0x01); /* write op */
do{ //wait i2cmpdone
if(hdmirx_rd_dwc(RA_HDMI_ISTS)&(1<<28)){
hdmirx_wr_dwc(RA_HDMI_ICLR, 1<<28);
break;
}
cnt++;
if(cnt>10000){
printk("[HDMIRX error]: %s(%x,%x,%x) timeout\n", __func__, 0x39, reg_address, data);
break;
}
}while(1);
if(hdmirx_log_flag & 0x2){
printk("Write PHY Reg 0x%08x <= 0x%08x\n", reg_address, data);
}
return error;
}
static void control_reset(unsigned char seq)
{
unsigned long data32;
if(seq==0){
//DWC reset default to be active, until reg HDMIRX_TOP_SW_RESET[0] is set to 0.
//hdmirx_rd_check_reg(HDMIRX_DEV_ID_TOP, HDMIRX_TOP_SW_RESET, 0x1, 0x0);
// Release IP reset
hdmirx_wr_top( HDMIRX_TOP_SW_RESET, 0x0);
// Enable functional modules
data32 = 0;
data32 |= 1 << 5; // [5] cec_enable
data32 |= 1 << 4; // [4] aud_enable
data32 |= 1 << 3; // [3] bus_enable
data32 |= 1 << 2; // [2] hdmi_enable
data32 |= 1 << 1; // [1] modet_enable
data32 |= 1 << 0; // [0] cfg_enable
hdmirx_wr_dwc(RA_DMI_DISABLE_IF, data32); // DEFAULT: {31'd0, 1'b0}
mdelay(1);
// Reset functional modules
hdmirx_wr_dwc(RA_DMI_SW_RST, 0x0000007F);
mdelay(1);
//hdmirx_rd_check_reg(HDMIRX_DEV_ID_DWC, HDMIRX_DWC_DMI_SW_RST, 0, 0);
// RX Reset
}
else{
data32 = 0;
data32 |= 0 << 5; // [5] cec_enable
data32 |= 0 << 4; // [4] aud_enable
data32 |= 0 << 3; // [3] bus_enable
data32 |= 0 << 2; // [2] hdmi_enable
data32 |= 0 << 1; // [1] modet_enable
data32 |= 1 << 0; // [0] cfg_enable
hdmirx_wr_dwc(RA_DMI_DISABLE_IF, data32); // DEFAULT: {31'd0, 1'b0}
mdelay(1);
//--------------------------------------------------------------------------
// Bring up RX
//--------------------------------------------------------------------------
data32 = 0;
data32 |= 1 << 5; // [5] cec_enable
data32 |= 1 << 4; // [4] aud_enable
data32 |= 1 << 3; // [3] bus_enable
data32 |= 1 << 2; // [2] hdmi_enable
data32 |= 1 << 1; // [1] modet_enable
data32 |= 1 << 0; // [0] cfg_enable
hdmirx_wr_dwc(RA_DMI_DISABLE_IF, data32); // DEFAULT: {31'd0, 1'b0}
mdelay(1);
}
}
static int packet_init(void)
{
int error = 0;
hdmirx_wr_dwc(RA_PDEC_CTRL, PFIFO_STORE_FILTER_EN|PD_FIFO_WE|PDEC_BCH_EN);
hdmirx_wr_dwc(RA_PDEC_ASP_CTRL, AUTO_VMUTE|AUTO_SPFLAT_MUTE);
return error;
}
void hdmirx_audio_enable(bool en)
{
unsigned int val = hdmirx_rd_dwc(RA_AUD_SAO_CTRL);
if (en) {
if (val != 1)
hdmirx_wr_dwc(RA_AUD_SAO_CTRL, 1);
} else {
if (val != 0x7ff)
hdmirx_wr_dwc(RA_AUD_SAO_CTRL, 0x7ff);
}
}
static void phy_init(int rx_port_sel, int dcm)
{
unsigned int data32;
// Configuring I2C to work in fastmode
hdmirx_wr_dwc( RA_I2CM_PHYG3_MODE, 0x1);
hdmirx_phy_pddq(1);
/* write timebase override and override enable */
hdmirx_wr_phy(OVL_PROT_CTRL, 0x2); //disable overload protect for Philips DVD
hdmirx_wr_phy(REG_HDMI_PHY_CMU_CONFIG,
(rx.phy.phy_cmu_config_force_val != 0) ? rx.phy.phy_cmu_config_force_val :
((rx.phy.lock_thres << 10) | (1 << 9) | (((1 << 9) - 1) & ((rx.phy.cfg_clk * 4) / 1000))));
data32 = 0;
data32 |= 0 << 15; // [15] mpll_short_power_up
data32 |= 0 << 13; // [14:13] mpll_mult
data32 |= 0 << 12; // [12] dis_off_lp
data32 |= rx.phy.fast_switching << 11; // [11] fast_switching
data32 |= 0 << 10; // [10] bypass_afe
data32 |= rx.phy.fsm_enhancement<< 9; // [9] fsm_enhancement
data32 |= 0 << 8; // [8] low_freq_eq
data32 |= 0 << 7; // [7] bypass_aligner
data32 |= dcm << 5; // [6:5] color_depth: 0=8-bit; 1=10-bit; 2=12-bit; 3=16-bit.
data32 |= 0 << 3; // [4:3] sel_tmdsclk: 0=Use chan0 clk; 1=Use chan1 clk; 2=Use chan2 clk; 3=Rsvd.
data32 |= rx.phy.port_select_ovr_en << 2; // [2] port_select_ovr_en
data32 |= rx_port_sel << 0; // [1:0] port_select_ovr
hdmirx_wr_phy( REG_HDMI_PHY_SYSTEM_CONFIG,
(rx.phy.phy_system_config_force_val != 0) ? rx.phy.phy_system_config_force_val : data32);
//phy clock config
hdmirx_phy_pddq(0);
}
void hdmirx_hw_config(void)
{
hdmirx_print("%s %d\n", __func__, rx.port);
WRITE_CBUS_REG(RESET0_REGISTER, 0x8); //reset HDMIRX module
clk_init();
hdmirx_wr_top(HDMIRX_TOP_INTR_MASKN, 0); //disable top interrupt gate
hdmirx_wr_top( HDMIRX_TOP_PORT_SEL, (1<<rx.port)); //EDID port select
control_reset(0);
hdmirx_interrupts_cfg(false); //disable dwc interrupt
if(hdcp_enable){
hdmi_rx_ctrl_hdcp_config(&rx.hdcp);
} else {
hdmirx_wr_bits_dwc( RA_HDCP_CTRL, HDCP_ENABLE, 0);
}
/*phy config*/
hdmirx_phy_restart();
hdmi_rx_phy_fast_switching(1);
phy_init(rx.port, 0); //port, dcm
/**/
/* control config */
control_init(rx.port);
audio_init();
packet_init();
hdmirx_audio_fifo_rst();
hdmirx_packet_fifo_rst();
/**/
control_reset(1);
/*enable irq */
hdmirx_wr_dwc(RA_HDMI_IEN_SET, CLK_CHANGE);
hdmirx_wr_top(HDMIRX_TOP_INTR_MASKN, 0x00001fff);
/**/
#ifndef USE_GPIO_FOR_HPD
hdmi_rx_ctrl_hpd(true);
hdmirx_wr_top( HDMIRX_TOP_HPD_PWR5V, (1<<5)|(1<<4)); //invert HDP output
#endif
/* wait at least 4 video frames (at 24Hz) : 167ms for the mode detection
recover the video mode */
mdelay(200);
/* Check If HDCP engine is in Idle state, if not wait for authentication time.
200ms is enough if no Ri errors */
if (hdmirx_rd_dwc(0xe0) != 0)
{
mdelay(200);
}
}
uint16_t hdmirx_rd_phy(uint8_t reg_address)
{
int cnt = 0;
//hdmirx_wr_dwc(RA_I2CM_PHYG3_SLAVE, 0x39);
hdmirx_wr_dwc(RA_I2CM_PHYG3_ADDRESS, reg_address);
hdmirx_wr_dwc(RA_I2CM_PHYG3_OPERATION, 0x02); /* read op */
do{ //wait i2cmpdone
if(hdmirx_rd_dwc(RA_HDMI_ISTS)&(1<<28)){
hdmirx_wr_dwc(RA_HDMI_ICLR, 1<<28);
break;
}
cnt++;
if(cnt>10000){
printk("[HDMIRX error]: %s(%x,%x) timeout\n", __func__, 0x39, reg_address);
break;
}
}while(1);
return (uint16_t)(hdmirx_rd_dwc(RA_I2CM_PHYG3_DATAI));
}
static void hdmi_rx_ctrl_hdcp_config( const struct hdmi_rx_ctrl_hdcp *hdcp)
{
int error = 0;
unsigned i = 0;
unsigned k = 0;
hdmirx_wr_bits_dwc( RA_HDCP_CTRL, HDCP_ENABLE, 0);
//hdmirx_wr_bits_dwc(ctx, RA_HDCP_CTRL, KEY_DECRYPT_ENABLE, 1);
hdmirx_wr_bits_dwc( RA_HDCP_CTRL, KEY_DECRYPT_ENABLE, 0);
hdmirx_wr_dwc(RA_HDCP_SEED, hdcp->seed);
for (i = 0; i < HDCP_KEYS_SIZE; i += 2) {
for (k = 0; k < HDCP_KEY_WR_TRIES; k++) {
if (hdmirx_rd_bits_dwc( RA_HDCP_STS, HDCP_KEY_WR_OK_STS) != 0) {
break;
}
}
if (k < HDCP_KEY_WR_TRIES) {
hdmirx_wr_dwc(RA_HDCP_KEY1, hdcp->keys[i + 0]);
hdmirx_wr_dwc(RA_HDCP_KEY0, hdcp->keys[i + 1]);
} else {
error = -EAGAIN;
break;
}
}
hdmirx_wr_dwc(RA_HDCP_BKSV1, hdcp->bksv[0]);
hdmirx_wr_dwc(RA_HDCP_BKSV0, hdcp->bksv[1]);
hdmirx_wr_bits_dwc( RA_HDCP_RPT_CTRL, REPEATER, hdcp->repeat? 1 : 0);
hdmirx_wr_dwc(RA_HDCP_RPT_BSTATUS, 0); /* nothing attached downstream */
hdmirx_wr_bits_dwc( RA_HDCP_CTRL, HDCP_ENABLE, 1);
}
static int audio_init(void)
{
int err = 0;
unsigned int data32;
//hdmirx_wr_bits_dwc(RA_AUD_MUTE_CTRL, AUD_MUTE_SEL, AUD_MUTE_FORCE_UN);
data32 = 0;
data32 |= 3 << 21; // [22:21] aport_shdw_ctrl
data32 |= 2 << 19; // [20:19] auto_aclk_mute
data32 |= 1 << 10; // [16:10] aud_mute_speed
data32 |= 1 << 7; // [7] aud_avmute_en
data32 |= 1 << 5; // [6:5] aud_mute_sel
data32 |= 1 << 3; // [4:3] aud_mute_mode
data32 |= 0 << 1; // [2:1] aud_ttone_fs_sel
data32 |= 0 << 0; // [0] testtone_en
hdmirx_wr_dwc( RA_AUD_MUTE_CTRL, data32); // DEFAULT: {9'd0, 2'd0, 2'd0, 2'd0, 7'd48, 2'd0, 1'b1, 2'd3, 2'd3, 2'd0, 1'b0}
data32 = 0;
data32 |= 0 << 4; // [11:4] audio_fmt_chg_thres
data32 |= 0 << 1; // [2:1] audio_fmt
data32 |= 0 << 0; // [0] audio_fmt_sel
hdmirx_wr_dwc( RA_AUD_PAO_CTRL, data32); // DEFAULT: {20'd0, 8'd176, 1'b0, 2'd0, 1'b0}
data32 = 0;
data32 |= 0 << 8; // [8] fc_lfe_exchg: 1=swap channel 3 and 4
hdmirx_wr_dwc( RA_PDEC_AIF_CTRL, data32); // DEFAULT: {23'd0, 1'b0, 8'd0}
data32 = 0;
data32 |= 0 << 2; // [4:2] deltacts_irqtrig
data32 |= 0 << 0; // [1:0] cts_n_meas_mode
hdmirx_wr_dwc( RA_PDEC_ACRM_CTRL, data32); // DEFAULT: {27'd0, 3'd0, 2'd1}
/* enable all outputs and select 32-bit for I2S */
hdmirx_wr_dwc(RA_AUD_SAO_CTRL, 1);
return err;
}
static int control_init(unsigned port)
{
int err = 0;
unsigned evaltime = 0;
evaltime = (rx.ctrl.md_clk * 4095) / 158000;
hdmirx_wr_dwc(RA_HDMI_OVR_CTRL, ~0); /* enable all */
hdmirx_wr_bits_dwc(RA_HDMI_SYNC_CTRL, VS_POL_ADJ_MODE, VS_POL_ADJ_AUTO);
hdmirx_wr_bits_dwc(RA_HDMI_SYNC_CTRL, HS_POL_ADJ_MODE, HS_POL_ADJ_AUTO);
hdmirx_wr_bits_dwc(RA_HDMI_CKM_EVLTM, EVAL_TIME, evaltime);
hdmirx_control_clk_range(TMDS_CLK_MIN, TMDS_CLK_MAX);
/* bit field shared between phy and controller */
hdmirx_wr_bits_dwc(RA_HDMI_PCB_CTRL, INPUT_SELECT, port);
hdmirx_wr_bits_dwc(RA_SNPS_PHYG3_CTRL, ((1 << 2) - 1) << 2, port);
control_init_more();
return err;
}
void hdmirx_wr_bits_dwc( uint16_t addr, uint32_t mask, uint32_t value)
{
hdmirx_wr_dwc(addr, set(hdmirx_rd_dwc(addr), mask, value));
}
int hdmirx_config_audio(void)
{
#define AUD_CLK_DELTA 2000
#define RX_8_CHANNEL 1 // 0=I2S 2-channel; 1=I2S 4 x 2-channel.
int err = 0;
unsigned long data32 = 0;
#if 1
data32 = 0;
data32 |= 0 << 9; // [9] force_afif_status:1=Use cntl_audfifo_status_cfg as fifo status; 0=Use detected afif_status.
data32 |= 1 << 8; // [8] afif_status_auto:1=Enable audio FIFO status auto-exit EMPTY/FULL, if FIFO level is back to LipSync; 0=Once enters EMPTY/FULL, never exits.
data32 |= 1 << 6; // [ 7: 6] Audio FIFO nominal level :0=s_total/4;1=s_total/8;2=s_total/16;3=s_total/32.
data32 |= 3 << 4; // [ 5: 4] Audio FIFO critical level:0=s_total/4;1=s_total/8;2=s_total/16;3=s_total/32.
data32 |= 0 << 3; // [3] afif_status_clr:1=Clear audio FIFO status to IDLE.
data32 |= rx.ctrl.acr_mode << 2; // [2] dig_acr_en
data32 |= 0 << 1; // [1] audmeas_clk_sel: 0=select aud_pll_clk; 1=select aud_acr_clk.
data32 |= rx.ctrl.acr_mode << 0; // [0] aud_clk_sel: 0=select aud_pll_clk; 1=select aud_acr_clk.
hdmirx_wr_top( HDMIRX_TOP_ACR_CNTL_STAT, data32);
//hdmirx_wr_dwc( RA_AUDPLL_GEN_CTS, manual_acr_cts);
//hdmirx_wr_dwc( RA_AUDPLL_GEN_N, manual_acr_n);
#if 0
// Force N&CTS to start with, will switch to received values later on, for simulation speed up.
data32 = 0;
data32 |= 1 << 4; // [4] cts_n_ref: 0=used decoded; 1=use manual N&CTS.
hdmirx_wr_dwc( RA_AUD_CLK_CTRL, data32);
#endif
data32 = 0;
data32 |= 0 << 28; // [28] pll_lock_filter_byp
data32 |= 0 << 24; // [27:24] pll_lock_toggle_div
hdmirx_wr_dwc( RA_AUD_PLL_CTRL, data32); // DEFAULT: {1'b0, 3'd0, 4'd6, 4'd3, 4'd8, 1'b0, 1'b0, 1'b1, 1'b0, 12'd0}
data32 = 0;
data32 |= 80 << 18; // [26:18] afif_th_start
data32 |= 8 << 9; // [17:9] afif_th_max
data32 |= 8 << 0; // [8:0] afif_th_min
hdmirx_wr_dwc( RA_AUD_FIFO_TH, data32);
data32 = 0;
data32 |= 1 << 16; // [16] afif_subpackets: 0=store all sp; 1=store only the ones' spX=1.
data32 |= 0 << 0; // [0] afif_init
hdmirx_wr_dwc( RA_AUD_FIFO_CTRL, data32); // DEFAULT: {13'd0, 2'd0, 1'b1, 15'd0, 1'b0}
data32 = 0;
data32 |= (RX_8_CHANNEL? 0x7 :0x0) << 8; // [10:8] ch_map[7:5]
data32 |= 1 << 7; // [7] ch_map_manual
data32 |= (RX_8_CHANNEL? 0x1f:0x3) << 2; // [6:2] ch_map[4:0]
data32 |= 1 << 0; // [1:0] aud_layout_ctrl:0/1=auto layout; 2=layout 0; 3=layout 1.
hdmirx_wr_dwc( RA_AUD_CHEXTRA_CTRL, data32); // DEFAULT: {24'd0, 1'b0, 5'd0, 2'd0}
#endif
/* amlogic HDMIRX audio module enable*/
WRITE_MPEG_REG(HHI_AUDCLK_PLL_CNTL, 0x60010000);
WRITE_MPEG_REG(HHI_AUDCLK_PLL_CNTL2, 0x814d3928);
WRITE_MPEG_REG(HHI_AUDCLK_PLL_CNTL3, 0x6b425012);
WRITE_MPEG_REG(HHI_AUDCLK_PLL_CNTL4, 0x101);
WRITE_MPEG_REG(HHI_AUDCLK_PLL_CNTL5, 0x8550d20);
if(rx.aud_info.audio_recovery_clock > (96000 + AUD_CLK_DELTA)){
if(rx.ctrl.tmds_clk2 <= 36000000) {
printk("tmds_clk2 <= 36000000\n");
WRITE_MPEG_REG(HHI_AUDCLK_PLL_CNTL6, 0x55013000);
} else if (rx.ctrl.tmds_clk2 <= 53000000) {
printk("tmds_clk2 <= 53000000\n");
WRITE_MPEG_REG(HHI_AUDCLK_PLL_CNTL6, 0x55053000);
} else {
printk("tmds_clk2 > 53000000\n");
WRITE_MPEG_REG(HHI_AUDCLK_PLL_CNTL6, 0x55153000);
}
} else {
printk("audio_recovery_clock > 98000\n");
WRITE_MPEG_REG(HHI_AUDCLK_PLL_CNTL6, 0x55153000);
}
WRITE_MPEG_REG(HHI_AUDCLK_PLL_CNTL, 0x00010000); //reset
/**/
#if 0
WRITE_MPEG_REG(AUDIN_SOURCE_SEL, (0 <<12) | // [14:12]cntl_hdmirx_chsts_sel: 0=Report chan1 status; 1=Report chan2 status; ...; 7=Report chan8 status.
(0xf<<8) | // [11:8] cntl_hdmirx_chsts_en
(1 <<4) | // [5:4] spdif_src_sel: 1=Select HDMIRX SPDIF output as AUDIN source
(2 << 0)); // [1:0] i2sin_src_sel: 2=Select HDMIRX I2S output as AUDIN source
#endif
return err;
}
static void control_init_more(void)
{
#define VSYNC_POLARITY 1 // TX VSYNC polarity: 0=low active; 1=high active.
unsigned long data32;
data32 = 0;
data32 |= 0 << 13; // [ 13] checksum_init_mode
data32 |= EDID_AUTO_CHECKSUM_ENABLE << 12; // [ 12] auto_checksum_enable
data32 |= EDID_AUTO_CEC_ENABLE << 11; // [ 11] auto_cec_enable
data32 |= 0 << 10; // [ 10] scl_stretch_trigger_config
data32 |= 0 << 9; // [ 9] force_scl_stretch_trigger
data32 |= 1 << 8; // [ 8] scl_stretch_enable
data32 |= EDID_CLK_DIVIDE_M1 << 0; // [ 7: 0] clk_divide_m1
hdmirx_wr_top(HDMIRX_TOP_EDID_GEN_CNTL, data32);
#if 0
data32 = 0;
data32 |= VSYNC_POLARITY << 3; // [4:3] vs_pol_adj_mode:0=invert input VS; 1=no invert; 2=auto convert to high active; 3=no invert.
data32 |= 2 << 1; // [2:1] hs_pol_adj_mode:0=invert input VS; 1=no invert; 2=auto convert to high active; 3=no invert.
hdmirx_wr_dwc( RA_HDMI_SYNC_CTRL, data32); // DEFAULT: {27'd0, 2'd0, 2'd0, 1'b0}
#endif
#define interlace_mode 1
data32 = 0;
data32 |= 1 << 4; // [4] v_offs_lin_mode
data32 |= 1 << 1; // [1] v_edge
data32 |= interlace_mode << 0; // [0] v_mode
hdmirx_wr_dwc( RA_MD_VCTRL, data32); // DEFAULT: {27'd0, 1'b0, 2'd0, 1'b1, 1'b0}
data32 = 0;
data32 |= 0 << 20; // [20] rg_block_off:1=Enable HS/VS/CTRL filtering during active video
data32 |= 1 << 19; // [19] block_off:1=Enable HS/VS/CTRL passing during active video
data32 |= 5 << 16; // [18:16] valid_mode
data32 |= 0 << 12; // [13:12] ctrl_filt_sens
data32 |= 3 << 10; // [11:10] vs_filt_sens
data32 |= 0 << 8; // [9:8] hs_filt_sens
data32 |= 2 << 6; // [7:6] de_measure_mode
data32 |= 0 << 5; // [5] de_regen
data32 |= 3 << 3; // [4:3] de_filter_sens
hdmirx_wr_dwc( RA_HDMI_ERRORA_PROTECT, data32); // DEFAULT: {11'd0, 1'b0, 1'b0, 3'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 1'b0, 2'd0, 3'd0}
data32 = 0;
data32 |= 0 << 8; // [10:8] hact_pix_ith
data32 |= 0 << 5; // [5] hact_pix_src
data32 |= 1 << 4; // [4] htot_pix_src
hdmirx_wr_dwc( RA_MD_HCTRL1, data32); // DEFAULT: {21'd0, 3'd1, 2'd0, 1'b0, 1'b1, 4'd0}
data32 = 0;
data32 |= 1 << 12; // [14:12] hs_clk_ith
data32 |= 7 << 8; // [10:8] htot32_clk_ith
data32 |= 1 << 5; // [5] vs_act_time
data32 |= 3 << 3; // [4:3] hs_act_time
data32 |= 0 << 0; // [1:0] h_start_pos
hdmirx_wr_dwc( RA_MD_HCTRL2, data32); // DEFAULT: {17'd0, 3'd2, 1'b0, 3'd1, 2'd0, 1'b0, 2'd0, 1'b0, 2'd2}
data32 = 0;
data32 |= 1 << 10; // [11:10] vofs_lin_ith
data32 |= 3 << 8; // [9:8] vact_lin_ith
data32 |= 0 << 6; // [7:6] vtot_lin_ith
data32 |= 7 << 3; // [5:3] vs_clk_ith
data32 |= 2 << 0; // [2:0] vtot_clk_ith
hdmirx_wr_dwc( RA_MD_VTH, data32); // DEFAULT: {20'd0, 2'd2, 2'd0, 2'd0, 3'd2, 3'd2}
data32 = 0;
data32 |= 1 << 2; // [2] fafielddet_en
data32 |= 0 << 0; // [1:0] field_pol_mode
hdmirx_wr_dwc( RA_MD_IL_POL, data32); // DEFAULT: {29'd0, 1'b0, 2'd0}
data32 = 0;
data32 |= 0 << 1; // [4:1] man_vid_derepeat
data32 |= 1 << 0; // [0] auto_derepeat
hdmirx_wr_dwc( RA_HDMI_RESMPL_CTRL, data32); // DEFAULT: {27'd0, 4'd0, 1'b1}
}
int hdmirx_interrupts_hpd( bool enable)
{
int error = 0;
if (enable) {
/* set enable */
hdmirx_wr_dwc(RA_PDEC_IEN_SET, DVIDET|AIF_CKS_CHG|AVI_CKS_CHG|VSI_CKS_CHG|PD_FIFO_NEW_ENTRY|PD_FIFO_OVERFL);
hdmirx_wr_dwc(RA_AUD_FIFO_IEN_SET, AFIF_OVERFL|AFIF_UNDERFL);
hdmirx_wr_dwc(RA_MD_IEN_SET, VIDEO_MODE);
hdmirx_wr_dwc(RA_HDMI_IEN_SET, AKSV_RCV|DCM_CURRENT_MODE_CHG);
} else {
/* clear enable */
hdmirx_wr_dwc(RA_PDEC_IEN_CLR, DVIDET|AIF_CKS_CHG|AVI_CKS_CHG|VSI_CKS_CHG|PD_FIFO_NEW_ENTRY|PD_FIFO_OVERFL);
hdmirx_wr_dwc(RA_AUD_FIFO_IEN_CLR, AFIF_OVERFL|AFIF_UNDERFL);
hdmirx_wr_dwc(RA_MD_IEN_CLR, VIDEO_MODE);
hdmirx_wr_dwc(RA_HDMI_IEN_CLR, AKSV_RCV|DCM_CURRENT_MODE_CHG);
/* clear status */
hdmirx_wr_dwc(RA_PDEC_ICLR, DVIDET|AIF_CKS_CHG|AVI_CKS_CHG|VSI_CKS_CHG|PD_FIFO_NEW_ENTRY|PD_FIFO_OVERFL);
hdmirx_wr_dwc(RA_AUD_FIFO_ICLR, AFIF_OVERFL|AFIF_UNDERFL);
hdmirx_wr_dwc(RA_MD_ICLR, VIDEO_MODE);
hdmirx_wr_dwc(RA_HDMI_ICLR, AKSV_RCV|DCM_CURRENT_MODE_CHG);
}
return error;
}
int hdmirx_interrupts_cfg( bool enable)
{
int error = 0;
if (enable) {
/* set enable */
hdmirx_wr_dwc(RA_PDEC_IEN_SET, ~0);
hdmirx_wr_dwc(RA_AUD_CLK_IEN_SET, ~0);
hdmirx_wr_dwc(RA_AUD_FIFO_IEN_SET, ~0);
hdmirx_wr_dwc(RA_MD_IEN_SET, ~0);
hdmirx_wr_dwc(RA_HDMI_IEN_SET, ~0);
} else {
/* clear enable */
hdmirx_wr_dwc(RA_PDEC_IEN_CLR, ~0);
hdmirx_wr_dwc(RA_AUD_CLK_IEN_CLR, ~0);
hdmirx_wr_dwc(RA_AUD_FIFO_IEN_CLR, ~0);
hdmirx_wr_dwc(RA_MD_IEN_CLR, ~0);
hdmirx_wr_dwc(RA_HDMI_IEN_CLR, ~0);
/* clear status */
hdmirx_wr_dwc(RA_PDEC_ICLR, ~0);
hdmirx_wr_dwc(RA_AUD_CLK_ICLR, ~0);
hdmirx_wr_dwc(RA_AUD_FIFO_ICLR, ~0);
hdmirx_wr_dwc(RA_MD_ICLR, ~0);
hdmirx_wr_dwc(RA_HDMI_ICLR, ~0);
}
return error;
}
void phy_init(int rx_port_sel, int dcm)
{
unsigned int data32;
// PDDQ = 1'b1; PHY_RESET = 1'b1;
data32 = 0;
data32 |= 1 << 6; // [6] physvsretmodez
data32 |= 1 << 4; // [5:4] cfgclkfreq
data32 |= rx_port_sel << 2; // [3:2] portselect
data32 |= 1 << 1; // [1] phypddq
data32 |= 1 << 0; // [0] phyreset
hdmirx_wr_dwc(RA_SNPS_PHYG3_CTRL, data32); // DEFAULT: {27'd0, 3'd0, 2'd1}
mdelay(1);
// PDDQ = 1'b1; PHY_RESET = 1'b0;
data32 = 0;
data32 |= 1 << 6; // [6] physvsretmodez
data32 |= 1 << 4; // [5:4] cfgclkfreq
data32 |= rx_port_sel << 2; // [3:2] portselect
data32 |= 1 << 1; // [1] phypddq
data32 |= 0 << 0; // [0] phyreset
hdmirx_wr_dwc(RA_SNPS_PHYG3_CTRL, data32); // DEFAULT: {27'd0, 3'd0, 2'd1}
// Configuring PHY's MPLL
hdmirx_wr_phy(MPLL_PARAMETERS2, 0x2594);
hdmirx_wr_phy(MPLL_PARAMETERS3, 0x395B);
hdmirx_wr_phy(MPLL_PARAMETERS4, 0x3723);
hdmirx_wr_phy(MPLL_PARAMETERS5, 0x54BC);
hdmirx_wr_phy(MPLL_PARAMETERS6, 0x3A9C);
hdmirx_wr_phy(MPLL_PARAMETERS7, 0x310E);
hdmirx_wr_phy(MPLL_PARAMETERS8, 0x2520);
// Configuring I2C to work in fastmode
hdmirx_wr_dwc(RA_I2CM_PHYG3_MODE, 0x1);
/* write timebase override and override enable */
hdmirx_wr_phy(OVL_PROT_CTRL, 0x2); //disable overload protect for Philips DVD
hdmirx_wr_phy(REG_HDMI_PHY_CMU_CONFIG,
(rx.phy.phy_cmu_config_force_val != 0) ? rx.phy.phy_cmu_config_force_val :
((rx.phy.lock_thres << 10) | (1 << 9) | (((1 << 9) - 1) & ((rx.phy.cfg_clk * 4) / 1000))));
data32 = 0;
data32 |= 0 << 15; // [15] mpll_short_power_up
data32 |= 0 << 13; // [14:13] mpll_mult
data32 |= 0 << 12; // [12] dis_off_lp
data32 |= rx.phy.fast_switching << 11; // [11] fast_switching
data32 |= 0 << 10; // [10] bypass_afe
data32 |= rx.phy.fsm_enhancement<< 9; // [9] fsm_enhancement
data32 |= 0 << 8; // [8] low_freq_eq
data32 |= 0 << 7; // [7] bypass_aligner
data32 |= dcm << 5; // [6:5] color_depth: 0=8-bit; 1=10-bit; 2=12-bit; 3=16-bit.
data32 |= 0 << 3; // [4:3] sel_tmdsclk: 0=Use chan0 clk; 1=Use chan1 clk; 2=Use chan2 clk; 3=Rsvd.
data32 |= rx.phy.port_select_ovr_en << 2; // [2] port_select_ovr_en
data32 |= rx_port_sel << 0; // [1:0] port_select_ovr
hdmirx_wr_phy(REG_HDMI_PHY_SYSTEM_CONFIG,
(rx.phy.phy_system_config_force_val != 0) ? rx.phy.phy_system_config_force_val : data32);
// PDDQ = 1'b0; PHY_RESET = 1'b0;
data32 = 0;
data32 |= 1 << 6; // [6] physvsretmodez
data32 |= 1 << 4; // [5:4] cfgclkfreq
data32 |= rx_port_sel << 2; // [3:2] portselect
data32 |= 0 << 1; // [1] phypddq
data32 |= 0 << 0; // [0] phyreset
hdmirx_wr_dwc(RA_SNPS_PHYG3_CTRL, data32); // DEFAULT: {27'd0, 3'd0, 2'd1}
}
