/* * Perform any BL1 specific platform actions. */ void bl1_early_platform_setup(void) { const size_t bl1_size = BL1_RAM_LIMIT - BL1_RAM_BASE; unsigned int id, uart_base; generic_delay_timer_init(); hikey960_read_boardid(&id); if (id == 5300) uart_base = PL011_UART5_BASE; else uart_base = PL011_UART6_BASE; /* Initialize the console to provide early debug support */ console_init(uart_base, PL011_UART_CLK_IN_HZ, PL011_BAUDRATE); /* Allow BL1 to see the whole Trusted RAM */ bl1_tzram_layout.total_base = BL1_RW_BASE; bl1_tzram_layout.total_size = BL1_RW_SIZE; /* Calculate how much RAM BL1 is using and how much remains free */ bl1_tzram_layout.free_base = BL1_RW_BASE; bl1_tzram_layout.free_size = BL1_RW_SIZE; reserve_mem(&bl1_tzram_layout.free_base, &bl1_tzram_layout.free_size, BL1_RAM_BASE, bl1_size); INFO("BL1: 0x%lx - 0x%lx [size = %lu]\n", BL1_RAM_BASE, BL1_RAM_LIMIT, bl1_size); }
static void hikey960_pinmux_init(void) { unsigned int id; hikey960_read_boardid(&id); if (id == 5301) { /* hikey960 hardware v2 */ /* GPIO150: LED */ mmio_write_32(IOMG_FIX_006_REG, 0); /* GPIO151: LED */ mmio_write_32(IOMG_FIX_007_REG, 0); /* GPIO189: LED */ mmio_write_32(IOMG_AO_011_REG, 0); /* GPIO190: LED */ mmio_write_32(IOMG_AO_012_REG, 0); /* GPIO46 */ mmio_write_32(IOMG_044_REG, 0); /* GPIO202 */ mmio_write_32(IOMG_AO_023_REG, 0); /* GPIO206 */ mmio_write_32(IOMG_AO_026_REG, 0); /* GPIO219 - PD pullup */ mmio_write_32(IOMG_AO_039_REG, 0); mmio_write_32(IOCG_AO_043_REG, 1 << 0); } /* GPIO005 - PMU SSI, 10mA */ mmio_write_32(IOCG_006_REG, 2 << 4); }
void bl2_early_platform_setup(meminfo_t *mem_layout) { unsigned int id, uart_base; generic_delay_timer_init(); hikey960_read_boardid(&id); if (id == 5300) uart_base = PL011_UART5_BASE; else uart_base = PL011_UART6_BASE; /* Initialize the console to provide early debug support */ console_init(uart_base, PL011_UART_CLK_IN_HZ, PL011_BAUDRATE); /* Setup the BL2 memory layout */ bl2_tzram_layout = *mem_layout; }
/* * Perform any BL1 specific platform actions. */ void bl1_early_platform_setup(void) { unsigned int id, uart_base; generic_delay_timer_init(); hikey960_read_boardid(&id); if (id == 5300) uart_base = PL011_UART5_BASE; else uart_base = PL011_UART6_BASE; /* Initialize the console to provide early debug support */ console_pl011_register(uart_base, PL011_UART_CLK_IN_HZ, PL011_BAUDRATE, &console); /* Allow BL1 to see the whole Trusted RAM */ bl1_tzram_layout.total_base = BL1_RW_BASE; bl1_tzram_layout.total_size = BL1_RW_SIZE; INFO("BL1: 0x%lx - 0x%lx [size = %lu]\n", BL1_RAM_BASE, BL1_RAM_LIMIT, BL1_RAM_LIMIT - BL1_RAM_BASE); /* bl1_size */ }