static void hi3660_clk_crgctrl_init(struct device_node *np) { struct hisi_clock_data *clk_data; int nr = ARRAY_SIZE(hi3660_fixed_rate_clks) + ARRAY_SIZE(hi3660_crgctrl_gate_sep_clks) + ARRAY_SIZE(hi3660_crgctrl_gate_clks) + ARRAY_SIZE(hi3660_crgctrl_mux_clks) + ARRAY_SIZE(hi3660_crg_fixed_factor_clks) + ARRAY_SIZE(hi3660_crgctrl_divider_clks); clk_data = hisi_clk_init(np, nr); if (!clk_data) return; hisi_clk_register_fixed_rate(hi3660_fixed_rate_clks, ARRAY_SIZE(hi3660_fixed_rate_clks), clk_data); hisi_clk_register_gate_sep(hi3660_crgctrl_gate_sep_clks, ARRAY_SIZE(hi3660_crgctrl_gate_sep_clks), clk_data); hisi_clk_register_gate(hi3660_crgctrl_gate_clks, ARRAY_SIZE(hi3660_crgctrl_gate_clks), clk_data); hisi_clk_register_mux(hi3660_crgctrl_mux_clks, ARRAY_SIZE(hi3660_crgctrl_mux_clks), clk_data); hisi_clk_register_fixed_factor(hi3660_crg_fixed_factor_clks, ARRAY_SIZE(hi3660_crg_fixed_factor_clks), clk_data); hisi_clk_register_divider(hi3660_crgctrl_divider_clks, ARRAY_SIZE(hi3660_crgctrl_divider_clks), clk_data); }
static void hi3660_clk_pctrl_init(struct device_node *np) { struct hisi_clock_data *clk_data; int nr = ARRAY_SIZE(hi3660_pctrl_gate_clks); clk_data = hisi_clk_init(np, nr); if (!clk_data) return; hisi_clk_register_gate(hi3660_pctrl_gate_clks, ARRAY_SIZE(hi3660_pctrl_gate_clks), clk_data); }
static void __init hip04_clk_init(struct device_node *np) { struct hisi_clock_data *clk_data; clk_data = hisi_clk_init(np, HIP04_NR_CLKS); if (!clk_data) return; hisi_clk_register_fixed_rate(hip04_fixed_rate_clks, ARRAY_SIZE(hip04_fixed_rate_clks), clk_data); }
static void __init hi6220_clk_power_init(struct device_node *np) { struct hisi_clock_data *clk_data; clk_data = hisi_clk_init(np, HI6220_POWER_NR_CLKS); if (!clk_data) return; hisi_clk_register_gate(hi6220_gate_clks_power, ARRAY_SIZE(hi6220_gate_clks_power), clk_data); hi6220_clk_register_divider(hi6220_div_clks_power, ARRAY_SIZE(hi6220_div_clks_power), clk_data); }
static void __init hi6220_clk_ao_init(struct device_node *np) { struct hisi_clock_data *clk_data_ao; clk_data_ao = hisi_clk_init(np, HI6220_AO_NR_CLKS); if (!clk_data_ao) return; hisi_clk_register_fixed_rate(hi6220_fixed_rate_clks, ARRAY_SIZE(hi6220_fixed_rate_clks), clk_data_ao); hisi_clk_register_fixed_factor(hi6220_fixed_factor_clks, ARRAY_SIZE(hi6220_fixed_factor_clks), clk_data_ao); hisi_clk_register_gate_sep(hi6220_separated_gate_clks_ao, ARRAY_SIZE(hi6220_separated_gate_clks_ao), clk_data_ao); }
static void __init hi6220_clk_media_init(struct device_node *np) { struct hisi_clock_data *clk_data; clk_data = hisi_clk_init(np, HI6220_MEDIA_NR_CLKS); if (!clk_data) return; hisi_clk_register_gate_sep(hi6220_separated_gate_clks_media, ARRAY_SIZE(hi6220_separated_gate_clks_media), clk_data); hisi_clk_register_mux(hi6220_mux_clks_media, ARRAY_SIZE(hi6220_mux_clks_media), clk_data); hi6220_clk_register_divider(hi6220_div_clks_media, ARRAY_SIZE(hi6220_div_clks_media), clk_data); }
static void __init hi6220_clk_sys_init(struct device_node *np) { struct hisi_clock_data *clk_data; clk_data = hisi_clk_init(np, HI6220_SYS_NR_CLKS); if (!clk_data) return; hisi_clk_register_gate(hi6220_reset_clks, ARRAY_SIZE(hi6220_reset_clks), clk_data); hisi_clk_register_gate_sep(hi6220_separated_gate_clks_sys, ARRAY_SIZE(hi6220_separated_gate_clks_sys), clk_data); hisi_clk_register_mux(hi6220_mux_clks_sys, ARRAY_SIZE(hi6220_mux_clks_sys), clk_data); hi6220_clk_register_divider(hi6220_div_clks_sys, ARRAY_SIZE(hi6220_div_clks_sys), clk_data); }
static void __init hi3620_clk_init(struct device_node *np) { struct hisi_clock_data *clk_data; clk_data = hisi_clk_init(np, HI3620_NR_CLKS); if (!clk_data) return; hisi_clk_register_fixed_rate(hi3620_fixed_rate_clks, ARRAY_SIZE(hi3620_fixed_rate_clks), clk_data); hisi_clk_register_fixed_factor(hi3620_fixed_factor_clks, ARRAY_SIZE(hi3620_fixed_factor_clks), clk_data); hisi_clk_register_mux(hi3620_mux_clks, ARRAY_SIZE(hi3620_mux_clks), clk_data); hisi_clk_register_divider(hi3620_div_clks, ARRAY_SIZE(hi3620_div_clks), clk_data); hisi_clk_register_gate_sep(hi3620_separated_gate_clks, ARRAY_SIZE(hi3620_separated_gate_clks), clk_data); }
static void __init hi6220_clk_sys_init(struct device_node *np) { struct hisi_clock_data *clk_data; clk_data = hisi_clk_init(np, HI6220_SYS_NR_CLKS); if (!clk_data) return; hisi_clk_register_gate_sep(hi6220_separated_gate_clks_sys, ARRAY_SIZE(hi6220_separated_gate_clks_sys), clk_data); hisi_clk_register_mux(hi6220_mux_clks_sys, ARRAY_SIZE(hi6220_mux_clks_sys), clk_data); hi6220_clk_register_divider(hi6220_div_clks_sys, ARRAY_SIZE(hi6220_div_clks_sys), clk_data); if (!clk_data_ao) return; /* enable high speed clock on UART1 mux */ clk_set_parent(clk_data->clk_data.clks[HI6220_UART1_SRC], clk_data_ao->clk_data.clks[HI6220_150M]); }