static void save_push_v1(struct nvhost_hwctx *nctx, struct nvhost_cdma *cdma)
{
struct host1x_hwctx *ctx = to_host1x_hwctx(nctx);
struct host1x_hwctx_handler *p = host1x_hwctx_handler(ctx);
/* wait for 3d idle */
nvhost_cdma_push(cdma,
nvhost_opcode_setclass(NV_GRAPHICS_3D_CLASS_ID, 0, 0),
nvhost_opcode_imm_incr_syncpt(
host1x_uclass_incr_syncpt_cond_op_done_v(),
p->syncpt));
nvhost_cdma_push(cdma,
nvhost_opcode_setclass(NV_HOST1X_CLASS_ID,
host1x_uclass_wait_syncpt_base_r(), 1),
nvhost_class_host_wait_syncpt_base(p->syncpt,
p->waitbase, 1));
/* back to 3d */
nvhost_cdma_push(cdma,
nvhost_opcode_setclass(NV_GRAPHICS_3D_CLASS_ID, 0, 0),
NVHOST_OPCODE_NOOP);
/* invalidate the FDC to prevent cache-coherency issues across GPUs
note that we assume FDC_CONTROL_0 is left in the reset state by all
contexts. the invalidate bit will clear itself, so the register
should be unchanged after this */
nvhost_cdma_push(cdma,
nvhost_opcode_imm(AR3D_FDC_CONTROL_0,
AR3D_FDC_CONTROL_0_RESET_VAL
| AR3D_FDC_CONTROL_0_INVALIDATE),
NVHOST_OPCODE_NOOP);
/* set register set 0 and 1 register read memory output addresses,
and send their reads to memory */
nvhost_cdma_push(cdma,
nvhost_opcode_imm(AR3D_GSHIM_WRITE_MASK, 2),
nvhost_opcode_imm(AR3D_GLOBAL_MEMORY_OUTPUT_READS, 1));
nvhost_cdma_push(cdma,
nvhost_opcode_nonincr(AR3D_DW_MEMORY_OUTPUT_ADDRESS, 1),
ctx->restore_phys + restore_set1_offset * 4);
nvhost_cdma_push(cdma,
nvhost_opcode_imm(AR3D_GSHIM_WRITE_MASK, 1),
nvhost_opcode_imm(AR3D_GLOBAL_MEMORY_OUTPUT_READS, 1));
nvhost_cdma_push(cdma,
nvhost_opcode_nonincr(AR3D_DW_MEMORY_OUTPUT_ADDRESS, 1),
ctx->restore_phys);
/* gather the save buffer */
nvhost_cdma_push_gather(cdma,
nvhost_get_host(nctx->channel->dev)->memmgr,
p->save_buf,
0,
nvhost_opcode_gather(p->save_size),
p->save_phys);
}
static void save_push_v0(struct nvhost_hwctx *nctx, struct nvhost_cdma *cdma)
{
struct host1x_hwctx *ctx = to_host1x_hwctx(nctx);
struct host1x_hwctx_handler *p = host1x_hwctx_handler(ctx);
nvhost_cdma_push_gather(cdma,
nvhost_get_host(nctx->channel->dev)->memmgr,
p->save_buf,
0,
nvhost_opcode_gather(p->save_size),
p->save_phys);
}
static void save_push_v1(struct nvhost_hwctx *nctx, struct nvhost_cdma *cdma)
{
struct host1x_hwctx *ctx = to_host1x_hwctx(nctx);
struct host1x_hwctx_handler *p = host1x_hwctx_handler(ctx);
/* wait for 3d idle */
nvhost_cdma_push(cdma,
nvhost_opcode_setclass(NV_GRAPHICS_3D_CLASS_ID, 0, 0),
nvhost_opcode_imm_incr_syncpt(
host1x_uclass_incr_syncpt_cond_op_done_v(),
p->h.syncpt));
nvhost_cdma_push(cdma,
nvhost_opcode_setclass(NV_HOST1X_CLASS_ID,
host1x_uclass_wait_syncpt_base_r(), 1),
nvhost_class_host_wait_syncpt_base(p->h.syncpt,
p->h.waitbase, 1));
/* back to 3d */
nvhost_cdma_push(cdma,
nvhost_opcode_setclass(NV_GRAPHICS_3D_CLASS_ID, 0, 0),
NVHOST_OPCODE_NOOP);
/* invalidate the FDC to prevent cache-coherency issues across GPUs
note that we assume FDC_CONTROL_0 is left in the reset state by all
contexts. the invalidate bit will clear itself, so the register
should be unchanged after this */
/* bug 990395 T114 HW no longer can automatically clear the invalidate
bit. Luckily that the ctx switching always happens on the push
buffer boundary, and 3d driver inserts a FDC flush & invalidate &
clear the invalidate bit in the beginning of the each push buffer.
So we do not need to explicitly clear the invalidate bit here. */
nvhost_cdma_push(cdma,
nvhost_opcode_imm(AR3D_FDC_CONTROL_0,
AR3D_FDC_CONTROL_0_RESET_VAL
| AR3D_FDC_CONTROL_0_INVALIDATE),
nvhost_opcode_imm(AR3D_GLOBAL_MEMORY_OUTPUT_READS, 1));
/* bug 972588 requires SW to clear the reg 0x403 and 0xe45 */
nvhost_cdma_push(cdma,
nvhost_opcode_imm(0xe45, 0),
nvhost_opcode_imm(0x403, 0));
nvhost_cdma_push(cdma,
nvhost_opcode_nonincr(AR3D_DW_MEMORY_OUTPUT_ADDRESS, 1),
ctx->restore_phys);
/* gather the save buffer */
nvhost_cdma_push_gather(cdma,
nvhost_get_host(nctx->channel->dev)->memmgr,
p->save_buf,
0,
nvhost_opcode_gather(p->save_size),
p->save_phys);
}
static void ctx3d_save_service(struct nvhost_hwctx *nctx)
{
struct host1x_hwctx *ctx = to_host1x_hwctx(nctx);
u32 *ptr = (u32 *)ctx->restore_virt + RESTORE_BEGIN_SIZE;
unsigned int pending = 0;
ptr = save_regs_v0(ptr, &pending, nctx->channel,
ctxsave_regs_3d_global,
ARRAY_SIZE(ctxsave_regs_3d_global));
wmb();
nvhost_syncpt_cpu_incr(&nvhost_get_host(nctx->channel->dev)->syncpt,
host1x_hwctx_handler(ctx)->syncpt);
}
static void save_push_v1(struct nvhost_hwctx *nctx, struct nvhost_cdma *cdma)
{
struct host1x_hwctx *ctx = to_host1x_hwctx(nctx);
struct host1x_hwctx_handler *p = host1x_hwctx_handler(ctx);
/* wait for 3d idle */
nvhost_cdma_push(cdma,
nvhost_opcode_setclass(NV_GRAPHICS_3D_CLASS_ID, 0, 0),
nvhost_opcode_imm_incr_syncpt(NV_SYNCPT_OP_DONE,
p->syncpt));
nvhost_cdma_push(cdma,
nvhost_opcode_setclass(NV_HOST1X_CLASS_ID,
NV_CLASS_HOST_WAIT_SYNCPT_BASE, 1),
nvhost_class_host_wait_syncpt_base(p->syncpt,
p->waitbase, 1));
/* back to 3d */
nvhost_cdma_push(cdma,
nvhost_opcode_setclass(NV_GRAPHICS_3D_CLASS_ID, 0, 0),
NVHOST_OPCODE_NOOP);
/* set register set 0 and 1 register read memory output addresses,
and send their reads to memory */
if (register_sets == 2) {
nvhost_cdma_push(cdma,
nvhost_opcode_imm(AR3D_GSHIM_WRITE_MASK, 2),
nvhost_opcode_imm(AR3D_GLOBAL_MEMORY_OUTPUT_READS,
1));
nvhost_cdma_push(cdma,
nvhost_opcode_nonincr(0x904, 1),
ctx->restore_phys + restore_set1_offset * 4);
}
nvhost_cdma_push(cdma,
nvhost_opcode_imm(AR3D_GSHIM_WRITE_MASK, 1),
nvhost_opcode_imm(AR3D_GLOBAL_MEMORY_OUTPUT_READS, 1));
nvhost_cdma_push(cdma,
nvhost_opcode_nonincr(AR3D_DW_MEMORY_OUTPUT_ADDRESS, 1),
ctx->restore_phys);
/* gather the save buffer */
nvhost_cdma_push_gather(cdma,
nvhost_get_host(nctx->channel->dev)->nvmap,
p->save_buf->handle,
0,
nvhost_opcode_gather(p->save_size),
p->save_phys);
}
