void hsi_driver_cancel_read_interrupt(struct hsi_channel *ch)
{
struct hsi_port *p = ch->hsi_port;
unsigned int port = p->port_number;
unsigned int channel = ch->channel_number;
void __iomem *base = p->hsi_controller->base;
hsi_outl_and(~HSI_HSR_DATAAVAILABLE(channel), base,
HSI_SYS_MPU_ENABLE_CH_REG(port, p->n_irq, channel));
hsi_reset_ch_read(ch);
}
/**
* hsi_driver_cancel_read_dma - Cancel an ongoing GDD [DMA] read for the
* specified hsi channel.
* @hsi_ch - pointer to the hsi_channel to cancel DMA read.
*
* hsi_controller lock must be held before calling this function.
*
* Return: -ENXIO : No DMA channel found for specified HSI channel
* -ECANCELED : DMA cancel success, data not available at expected
* address.
* 0 : DMA transfer is already over, data already available at
* expected address.
*
* Note: whatever returned value, read callback will not be called after cancel.
*/
int hsi_driver_cancel_read_dma(struct hsi_channel *hsi_ch)
{
int lch = hsi_ch->read_data.lch;
struct hsi_dev *hsi_ctrl = hsi_ch->hsi_port->hsi_controller;
u16 ccr, gdd_csr;
u32 status_reg;
dma_addr_t dma_h;
size_t size;
/* Re-enable interrupts for polling if needed */
if (hsi_ch->flags & HSI_CH_RX_POLL)
hsi_driver_enable_read_interrupt(hsi_ch, NULL);
if (lch < 0) {
dev_err(&hsi_ch->dev->device, "No DMA channel found for HSI "
"channel %d\n", hsi_ch->channel_number);
return -ENXIO;
}
ccr = hsi_inw(hsi_ctrl->base, HSI_GDD_CCR_REG(lch));
if (!(ccr & HSI_CCR_ENABLE)) {
dev_dbg(&hsi_ch->dev->device, "Read cancel on not "
"enabled logical channel %d CCR REG 0x%04X\n",
lch, ccr);
}
status_reg = hsi_inl(hsi_ctrl->base, HSI_SYS_GDD_MPU_IRQ_STATUS_REG);
status_reg &= hsi_inl(hsi_ctrl->base, HSI_SYS_GDD_MPU_IRQ_ENABLE_REG);
hsi_outw_and(~HSI_CCR_ENABLE, hsi_ctrl->base, HSI_GDD_CCR_REG(lch));
/* Clear CSR register by reading it, as it is cleared automaticaly */
/* by HW after SW read */
gdd_csr = hsi_inw(hsi_ctrl->base, HSI_GDD_CSR_REG(lch));
hsi_outl_and(~HSI_GDD_LCH(lch), hsi_ctrl->base,
HSI_SYS_GDD_MPU_IRQ_ENABLE_REG);
hsi_outl(HSI_GDD_LCH(lch), hsi_ctrl->base,
HSI_SYS_GDD_MPU_IRQ_STATUS_REG);
/* Unmap DMA region - Access to the buffer is now safe */
dma_h = hsi_inl(hsi_ctrl->base, HSI_GDD_CDSA_REG(lch));
size = hsi_inw(hsi_ctrl->base, HSI_GDD_CEN_REG(lch)) * 4;
dma_unmap_single(hsi_ctrl->dev, dma_h, size, DMA_FROM_DEVICE);
hsi_reset_ch_read(hsi_ch);
return status_reg & HSI_GDD_LCH(lch) ? 0 : -ECANCELED;
}
static void do_channel_rx(struct hsi_channel *ch)
{
struct hsi_dev *hsi_ctrl = ch->hsi_port->hsi_controller;
void __iomem *base = ch->hsi_port->hsi_controller->base;
unsigned int n_ch;
unsigned int n_p;
unsigned int irq;
long buff_offset;
int rx_poll = 0;
int data_read = 0;
n_ch = ch->channel_number;
n_p = ch->hsi_port->port_number;
irq = ch->hsi_port->n_irq;
spin_lock(&hsi_ctrl->lock);
if (ch->flags & HSI_CH_RX_POLL)
rx_poll = 1;
if (ch->read_data.addr) {
buff_offset = hsi_hsr_buffer_reg(hsi_ctrl, n_p, n_ch);
if (buff_offset >= 0) {
data_read = 1;
*(ch->read_data.addr) = hsi_inl(base, buff_offset);
}
}
hsi_outl_and(~HSI_HSR_DATAAVAILABLE(n_ch), base,
HSI_SYS_MPU_ENABLE_CH_REG(n_p, irq, n_ch));
hsi_reset_ch_read(ch);
spin_unlock(&hsi_ctrl->lock);
if (rx_poll)
hsi_port_event_handler(ch->hsi_port,
HSI_EVENT_HSR_DATAAVAILABLE, (void *)n_ch);
if (data_read)
(*ch->read_done)(ch->dev, 1);
}
/**
* hsi_driver_cancel_read_interrupt - Cancel pending read interrupt.
* @dev - hsi device channel where to cancel the pending interrupt.
*
* Return: -ECANCELED : read cancel success data not available at expected
* address.
* 0 : transfer is already over, data already available at expected
* address.
*
* Note: whatever returned value, read callback will not be called after cancel.
*/
int hsi_driver_cancel_read_interrupt(struct hsi_channel *ch)
{
struct hsi_port *p = ch->hsi_port;
unsigned int port = p->port_number;
unsigned int channel = ch->channel_number;
void __iomem *base = p->hsi_controller->base;
u32 status_reg;
status_reg = hsi_inl(base,
HSI_SYS_MPU_ENABLE_CH_REG(port, p->n_irq, channel));
if (!(status_reg & HSI_HSR_DATAAVAILABLE(channel))) {
dev_dbg(&ch->dev->device, "Read cancel on not "
"enabled channel %d ENABLE REG 0x%08X", channel,
status_reg);
}
status_reg &= hsi_inl(base,
HSI_SYS_MPU_STATUS_CH_REG(port, p->n_irq, channel));
hsi_outl_and(~HSI_HSR_DATAAVAILABLE(channel), base,
HSI_SYS_MPU_ENABLE_CH_REG(port, p->n_irq, channel));
hsi_reset_ch_read(ch);
return status_reg & HSI_HSR_DATAAVAILABLE(channel) ? 0 : -ECANCELED;
}
/* HSR_AVAILABLE interrupt processing */
static void hsi_do_channel_rx(struct hsi_channel *ch)
{
struct hsi_dev *hsi_ctrl = ch->hsi_port->hsi_controller;
void __iomem *base = ch->hsi_port->hsi_controller->base;
unsigned int n_ch;
unsigned int n_p;
unsigned int irq;
long buff_offset;
int rx_poll = 0;
int data_read = 0;
int fifo, fifo_words_avail;
n_ch = ch->channel_number;
n_p = ch->hsi_port->port_number;
irq = ch->hsi_port->n_irq;
dev_dbg(hsi_ctrl->dev,
"Data Available interrupt for channel %d.\n", n_ch);
/* Check if there is data in FIFO available for reading */
if (hsi_driver_device_is_hsi(to_platform_device(hsi_ctrl->dev))) {
fifo = hsi_fifo_get_id(hsi_ctrl, n_ch, n_p);
if (unlikely(fifo < 0)) {
dev_err(hsi_ctrl->dev, "No valid FIFO id found for "
"channel %d.\n", n_ch);
return;
}
fifo_words_avail = hsi_get_rx_fifo_occupancy(hsi_ctrl, fifo);
if (!fifo_words_avail) {
dev_dbg(hsi_ctrl->dev,
"WARNING: RX FIFO %d empty before CPU copy\n",
fifo);
/* Do not disable interrupt becaue another interrupt */
/* can still come, this time with a real frame. */
return;
}
}
/* Disable interrupts if not needed for polling */
if (!(ch->flags & HSI_CH_RX_POLL))
hsi_driver_disable_read_interrupt(ch);
/*
* Check race condition: RX transmission initiated but DMA transmission
* already started - acknowledge then ignore interrupt occurence
*/
if (ch->read_data.lch != -1) {
dev_warn(hsi_ctrl->dev,
"Race condition between RX Int ch %d and DMA %0x\n",
n_ch, ch->read_data.lch);
goto done;
}
if (ch->flags & HSI_CH_RX_POLL)
rx_poll = 1;
if (ch->read_data.addr) {
buff_offset = hsi_hsr_buffer_reg(hsi_ctrl, n_p, n_ch);
if (buff_offset >= 0) {
data_read = 1;
*(ch->read_data.addr) = hsi_inl(base, buff_offset);
}
}
hsi_reset_ch_read(ch);
done:
if (rx_poll) {
spin_unlock(&hsi_ctrl->lock);
hsi_port_event_handler(ch->hsi_port,
HSI_EVENT_HSR_DATAAVAILABLE,
(void *)n_ch);
spin_lock(&hsi_ctrl->lock);
}
if (data_read) {
spin_unlock(&hsi_ctrl->lock);
dev_dbg(hsi_ctrl->dev, "Calling ch %d read callback.\n", n_ch);
(*ch->read_done) (ch->dev, 1);
spin_lock(&hsi_ctrl->lock);
}
}
static void do_hsi_gdd_lch(struct hsi_dev *hsi_ctrl, unsigned int gdd_lch)
{
void __iomem *base = hsi_ctrl->base;
struct platform_device *pdev = to_platform_device(hsi_ctrl->dev);
struct hsi_channel *ch;
unsigned int port;
unsigned int channel;
unsigned int is_read_path;
u32 gdd_csr;
dma_addr_t dma_h;
size_t size;
int fifo, fifo_words_avail;
if (hsi_get_info_from_gdd_lch(hsi_ctrl, gdd_lch, &port, &channel,
&is_read_path) < 0) {
dev_err(hsi_ctrl->dev, "Unable to match the DMA channel %d with"
" an HSI channel\n", gdd_lch);
return;
} else {
dev_dbg(hsi_ctrl->dev, "DMA event on gdd_lch=%d => port=%d, "
"channel=%d, read=%d\n", gdd_lch, port, channel,
is_read_path);
}
hsi_outl_and(~HSI_GDD_LCH(gdd_lch), base,
HSI_SYS_GDD_MPU_IRQ_ENABLE_REG);
/* Warning : CSR register is cleared automaticaly by HW after SW read */
gdd_csr = hsi_inw(base, HSI_GDD_CSR_REG(gdd_lch));
if (!(gdd_csr & HSI_CSR_TOUT)) {
if (is_read_path) { /* Read path */
dma_h = hsi_inl(base, HSI_GDD_CDSA_REG(gdd_lch));
size = hsi_inw(base, HSI_GDD_CEN_REG(gdd_lch)) * 4;
dma_sync_single_for_cpu(hsi_ctrl->dev, dma_h, size,
DMA_FROM_DEVICE);
dma_unmap_single(hsi_ctrl->dev, dma_h, size,
DMA_FROM_DEVICE);
ch = hsi_ctrl_get_ch(hsi_ctrl, port, channel);
hsi_reset_ch_read(ch);
dev_dbg(hsi_ctrl->dev, "Calling ch %d read callback "
"(size %d).\n", channel, size/4);
spin_unlock(&hsi_ctrl->lock);
ch->read_done(ch->dev, size / 4);
spin_lock(&hsi_ctrl->lock);
/* Check if FIFO is correctly emptied */
if (hsi_driver_device_is_hsi(pdev)) {
fifo = hsi_fifo_get_id(hsi_ctrl, channel, port);
if (unlikely(fifo < 0)) {
dev_err(hsi_ctrl->dev, "No valid FIFO "
"id found for channel %d.\n",
channel);
return;
}
fifo_words_avail =
hsi_get_rx_fifo_occupancy(hsi_ctrl,
fifo);
if (fifo_words_avail)
dev_dbg(hsi_ctrl->dev,
"FIFO %d not empty "
"after DMA copy, remaining "
"%d/%d frames\n",
fifo, fifo_words_avail,
HSI_HSR_FIFO_SIZE);
}
/* Re-enable interrupts for polling if needed */
if (ch->flags & HSI_CH_RX_POLL)
hsi_driver_enable_read_interrupt(ch, NULL);
} else { /* Write path */
dma_h = hsi_inl(base, HSI_GDD_CSSA_REG(gdd_lch));
size = hsi_inw(base, HSI_GDD_CEN_REG(gdd_lch)) * 4;
dma_unmap_single(hsi_ctrl->dev, dma_h, size,
DMA_TO_DEVICE);
ch = hsi_ctrl_get_ch(hsi_ctrl, port, channel);
hsi_reset_ch_write(ch);
dev_dbg(hsi_ctrl->dev, "Calling ch %d write callback "
"(size %d).\n", channel, size/4);
spin_unlock(&hsi_ctrl->lock);
ch->write_done(ch->dev, size / 4);
spin_lock(&hsi_ctrl->lock);
}
} else {
dev_err(hsi_ctrl->dev, "Time-out overflow Error on GDD transfer"
" on gdd channel %d\n", gdd_lch);
spin_unlock(&hsi_ctrl->lock);
/* TODO : need to perform a DMA soft reset */
hsi_port_event_handler(&hsi_ctrl->hsi_port[port - 1],
HSI_EVENT_ERROR, NULL);
spin_lock(&hsi_ctrl->lock);
}
}
