static int hw_atl_utils_fw_upload_dwords(struct aq_hw_s *self, u32 a, u32 *p, u32 cnt) { int err = 0; bool is_locked; is_locked = hw_atl_reg_glb_cpu_sem_get(self, HW_ATL_FW_SM_RAM); if (!is_locked) { err = -ETIME; goto err_exit; } aq_hw_write_reg(self, 0x00000208U, a); for (++cnt; --cnt;) { u32 i = 0U; aq_hw_write_reg(self, 0x0000020CU, *(p++)); aq_hw_write_reg(self, 0x00000200U, 0xC000U); for (i = 1024U; (0x100U & aq_hw_read_reg(self, 0x00000200U)) && --i;) { } } hw_atl_reg_glb_cpu_sem_set(self, 1U, HW_ATL_FW_SM_RAM); err_exit: return err; }
int hw_atl_utils_fw_downld_dwords(struct aq_hw_s *self, u32 a, u32 *p, u32 cnt) { int err = 0; AQ_HW_WAIT_FOR(hw_atl_reg_glb_cpu_sem_get(self, HW_ATL_FW_SM_RAM) == 1U, 1U, 10000U); if (err < 0) { bool is_locked; hw_atl_reg_glb_cpu_sem_set(self, 1U, HW_ATL_FW_SM_RAM); is_locked = hw_atl_reg_glb_cpu_sem_get(self, HW_ATL_FW_SM_RAM); if (!is_locked) { err = -ETIMEDOUT; goto err_exit; } } aq_hw_write_reg(self, HW_ATL_MIF_ADDR, a); for (++cnt; --cnt && !err;) { aq_hw_write_reg(self, HW_ATL_MIF_CMD, 0x00008000U); if (IS_CHIP_FEATURE(REVISION_B1)) AQ_HW_WAIT_FOR(a != aq_hw_read_reg(self, HW_ATL_MIF_ADDR), 1, 1000U); else AQ_HW_WAIT_FOR(!(0x100 & aq_hw_read_reg(self, HW_ATL_MIF_CMD)), 1, 1000U); *(p++) = aq_hw_read_reg(self, HW_ATL_MIF_VAL); a += 4; } hw_atl_reg_glb_cpu_sem_set(self, 1U, HW_ATL_FW_SM_RAM); err_exit: return err; }
int hw_atl_utils_fw_downld_dwords(struct aq_hw_s *self, u32 a, u32 *p, u32 cnt) { int err = 0; AQ_HW_WAIT_FOR(hw_atl_reg_glb_cpu_sem_get(self, HW_ATL_FW_SM_RAM) == 1U, 1U, 10000U); if (err < 0) { bool is_locked; hw_atl_reg_glb_cpu_sem_set(self, 1U, HW_ATL_FW_SM_RAM); is_locked = hw_atl_reg_glb_cpu_sem_get(self, HW_ATL_FW_SM_RAM); if (!is_locked) { err = -ETIME; goto err_exit; } } aq_hw_write_reg(self, 0x00000208U, a); for (++cnt; --cnt;) { u32 i = 0U; aq_hw_write_reg(self, 0x00000200U, 0x00008000U); for (i = 1024U; (0x100U & aq_hw_read_reg(self, 0x00000200U)) && --i;) { } *(p++) = aq_hw_read_reg(self, 0x0000020CU); } hw_atl_reg_glb_cpu_sem_set(self, 1U, HW_ATL_FW_SM_RAM); err_exit: return err; }
int hw_atl_utils_fw_upload_dwords(struct aq_hw_s *self, u32 a, u32 *p, u32 cnt) { int err = 0; bool is_locked; is_locked = hw_atl_reg_glb_cpu_sem_get(self, HW_ATL_FW_SM_RAM); if (!is_locked) { err = -ETIMEDOUT; goto err_exit; } if (IS_CHIP_FEATURE(REVISION_B1)) { u32 offset = 0; for (; offset < cnt; ++offset) { aq_hw_write_reg(self, 0x328, p[offset]); aq_hw_write_reg(self, 0x32C, (0x80000000 | (0xFFFF & (offset * 4)))); hw_atl_mcp_up_force_intr_set(self, 1); /* 1000 times by 10us = 10ms */ AQ_HW_WAIT_FOR((aq_hw_read_reg(self, 0x32C) & 0xF0000000) != 0x80000000, 10, 1000); } } else { u32 offset = 0; aq_hw_write_reg(self, 0x208, a); for (; offset < cnt; ++offset) { aq_hw_write_reg(self, 0x20C, p[offset]); aq_hw_write_reg(self, 0x200, 0xC000); AQ_HW_WAIT_FOR((aq_hw_read_reg(self, 0x200U) & 0x100) == 0, 10, 1000); } } hw_atl_reg_glb_cpu_sem_set(self, 1U, HW_ATL_FW_SM_RAM); err_exit: return err; }