static unsigned long hdmi_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct hdmi_pll_8960 *pll = hw_clk_to_pll(hw); return pll->pixclk; }
/* * DSI PLL Helper functions */ long msm_dsi_pll_helper_clk_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { struct msm_dsi_pll *pll = hw_clk_to_pll(hw); if (rate < pll->min_rate) return pll->min_rate; else if (rate > pll->max_rate) return pll->max_rate; else return rate; }
static int hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct hdmi_pll_8960 *pll = hw_clk_to_pll(hw); const struct pll_rate *pll_rate = find_rate(rate); int i; DBG("rate=%lu", rate); for (i = 0; i < pll_rate->num_reg; i++) pll_write(pll, pll_rate->conf[i].reg, pll_rate->conf[i].val); pll->pixclk = rate; return 0; }
static void hdmi_pll_disable(struct clk_hw *hw) { struct hdmi_pll_8960 *pll = hw_clk_to_pll(hw); struct hdmi_phy *phy = pll_get_phy(pll); unsigned int val; DBG(""); val = hdmi_phy_read(phy, REG_HDMI_8960_PHY_REG12); val &= ~HDMI_8960_PHY_REG12_PWRDN_B; hdmi_phy_write(phy, REG_HDMI_8960_PHY_REG12, val); val = pll_read(pll, REG_HDMI_8960_PHY_PLL_PWRDN_B); val |= HDMI_8960_PHY_REG12_SW_RESET; val &= ~HDMI_8960_PHY_REG12_PWRDN_B; pll_write(pll, REG_HDMI_8960_PHY_PLL_PWRDN_B, val); /* Make sure HDMI PHY/PLL are powered down */ mb(); }
static int hdmi_pll_enable(struct clk_hw *hw) { struct hdmi_pll_8960 *pll = hw_clk_to_pll(hw); struct hdmi_phy *phy = pll_get_phy(pll); int timeout_count, pll_lock_retry = 10; unsigned int val; DBG(""); /* Assert PLL S/W reset */ pll_write(pll, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2, 0x8d); pll_write(pll, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG0, 0x10); pll_write(pll, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG1, 0x1a); /* Wait for a short time before de-asserting * to allow the hardware to complete its job. * This much of delay should be fine for hardware * to assert and de-assert. */ udelay(10); /* De-assert PLL S/W reset */ pll_write(pll, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2, 0x0d); val = hdmi_phy_read(phy, REG_HDMI_8960_PHY_REG12); val |= HDMI_8960_PHY_REG12_SW_RESET; /* Assert PHY S/W reset */ hdmi_phy_write(phy, REG_HDMI_8960_PHY_REG12, val); val &= ~HDMI_8960_PHY_REG12_SW_RESET; /* * Wait for a short time before de-asserting to allow the hardware to * complete its job. This much of delay should be fine for hardware to * assert and de-assert. */ udelay(10); /* De-assert PHY S/W reset */ hdmi_phy_write(phy, REG_HDMI_8960_PHY_REG12, val); hdmi_phy_write(phy, REG_HDMI_8960_PHY_REG2, 0x3f); val = hdmi_phy_read(phy, REG_HDMI_8960_PHY_REG12); val |= HDMI_8960_PHY_REG12_PWRDN_B; hdmi_phy_write(phy, REG_HDMI_8960_PHY_REG12, val); /* Wait 10 us for enabling global power for PHY */ mb(); udelay(10); val = pll_read(pll, REG_HDMI_8960_PHY_PLL_PWRDN_B); val |= HDMI_8960_PHY_PLL_PWRDN_B_PLL_PWRDN_B; val &= ~HDMI_8960_PHY_PLL_PWRDN_B_PD_PLL; pll_write(pll, REG_HDMI_8960_PHY_PLL_PWRDN_B, val); hdmi_phy_write(phy, REG_HDMI_8960_PHY_REG2, 0x80); timeout_count = 1000; while (--pll_lock_retry > 0) { /* are we there yet? */ val = pll_read(pll, REG_HDMI_8960_PHY_PLL_STATUS0); if (val & HDMI_8960_PHY_PLL_STATUS0_PLL_LOCK) break; udelay(1); if (--timeout_count > 0) continue; /* * PLL has still not locked. * Do a software reset and try again * Assert PLL S/W reset first */ pll_write(pll, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2, 0x8d); udelay(10); pll_write(pll, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2, 0x0d); /* * Wait for a short duration for the PLL calibration * before checking if the PLL gets locked */ udelay(350); timeout_count = 1000; } return 0; }
void msm_dsi_pll_helper_clk_unprepare(struct clk_hw *hw) { struct msm_dsi_pll *pll = hw_clk_to_pll(hw); dsi_pll_disable(pll); }
int msm_dsi_pll_helper_clk_prepare(struct clk_hw *hw) { struct msm_dsi_pll *pll = hw_clk_to_pll(hw); return dsi_pll_enable(pll); }
/* * Clock Callbacks */ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct msm_dsi_pll *pll = hw_clk_to_pll(hw); struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); struct device *dev = &pll_28nm->pdev->dev; void __iomem *base = pll_28nm->mmio; unsigned long div_fbx1000, gen_vco_clk; u32 refclk_cfg, frac_n_mode, frac_n_value; u32 sdm_cfg0, sdm_cfg1, sdm_cfg2, sdm_cfg3; u32 cal_cfg10, cal_cfg11; u32 rem; int i; VERB("rate=%lu, parent's=%lu", rate, parent_rate); /* Force postdiv2 to be div-4 */ pll_write(base + REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG, 3); /* Configure the Loop filter resistance */ for (i = 0; i < LPFR_LUT_SIZE; i++) if (rate <= lpfr_lut[i].vco_rate) break; if (i == LPFR_LUT_SIZE) { dev_err(dev, "unable to get loop filter resistance. vco=%lu\n", rate); return -EINVAL; } pll_write(base + REG_DSI_28nm_PHY_PLL_LPFR_CFG, lpfr_lut[i].resistance); /* Loop filter capacitance values : c1 and c2 */ pll_write(base + REG_DSI_28nm_PHY_PLL_LPFC1_CFG, 0x70); pll_write(base + REG_DSI_28nm_PHY_PLL_LPFC2_CFG, 0x15); rem = rate % VCO_REF_CLK_RATE; if (rem) { refclk_cfg = DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR; frac_n_mode = 1; div_fbx1000 = rate / (VCO_REF_CLK_RATE / 500); gen_vco_clk = div_fbx1000 * (VCO_REF_CLK_RATE / 500); } else { refclk_cfg = 0x0; frac_n_mode = 0; div_fbx1000 = rate / (VCO_REF_CLK_RATE / 1000); gen_vco_clk = div_fbx1000 * (VCO_REF_CLK_RATE / 1000); } DBG("refclk_cfg = %d", refclk_cfg); rem = div_fbx1000 % 1000; frac_n_value = (rem << 16) / 1000; DBG("div_fb = %lu", div_fbx1000); DBG("frac_n_value = %d", frac_n_value); DBG("Generated VCO Clock: %lu", gen_vco_clk); rem = 0; sdm_cfg1 = pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1); sdm_cfg1 &= ~DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK; if (frac_n_mode) { sdm_cfg0 = 0x0; sdm_cfg0 |= DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV(0); sdm_cfg1 |= DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET( (u32)(((div_fbx1000 / 1000) & 0x3f) - 1)); sdm_cfg3 = frac_n_value >> 8; sdm_cfg2 = frac_n_value & 0xff; } else {