static int i2c_stop(void)
{
unsigned long iicstat = 0;
iicstat = IICSTAT;
iicstat &= ~(1 << 5);
IICSTAT = iicstat; // generate stop signal
i2c_disable_irq();
}
/*
* Interrupt handler for I2C error conditions. Aborts any pending I2C
* transactions.
*/
void _i2c_irq_error_handler(i2c_dev *dev) {
I2C_CRUMB(ERROR_ENTRY, dev->regs->SR1, dev->regs->SR2);
dev->error_flags = dev->regs->SR1 & (I2C_SR1_BERR |
I2C_SR1_ARLO |
I2C_SR1_AF |
I2C_SR1_OVR);
/* Are we in slave mode? */
if ((dev->regs->SR2 & I2C_SR2_MSL) != I2C_SR2_MSL) {
/* Check to see if the master device did a NAK on the last bit
* This is perfectly valid for a master to do this on the bus.
* We ignore this. Any further error processing takes us into dead
* loop waiting for the stop condition that will never arrive
*/
if (dev->regs->SR1 & I2C_SR1_AF) {
/* Clear flags */
dev->regs->SR1 = 0;
dev->regs->SR2 = 0;
/* We need to write something to CR1 to clear the flag.
* This isn't really mentioned but seems important */
i2c_enable_ack(dev);
if (dev->state == I2C_STATE_SL_RX &&
dev->config_flags & I2C_SLAVE_USE_RX_BUFFER &&
dev->i2c_slave_msg->xferred > 0) {
/* Call the callback with the contents of the data */
if (dev->i2c_slave_recv_callback != NULL) (*(dev->i2c_slave_recv_callback))(dev->i2c_slave_msg);
}
dev->state = I2C_STATE_IDLE;
return;
}
/* Catch any other strange errors while in slave mode.
* I have seen BERR caused by an over fast master device
* as well as several overflows and arbitration failures.
* We are going to reset SR flags and carry on at this point which
* is not the best thing to do, but stops the bus locking up completely
* If we carry on below and send the stop bit, the code spins forever */
/* Clear flags */
dev->regs->SR1 = 0;
dev->regs->SR2 = 0;
dev->state = I2C_STATE_IDLE;
return;
}
/* Clear flags */
dev->regs->SR1 = 0;
dev->regs->SR2 = 0;
i2c_stop_condition(dev);
i2c_disable_irq(dev, I2C_IRQ_BUFFER | I2C_IRQ_EVENT | I2C_IRQ_ERROR);
dev->state = I2C_STATE_ERROR;
}
/**
* @brief Interrupt handler for I2C error conditions
* @param dev I2C device
* @sideeffect Aborts any pending I2C transactions
*/
static void i2c_irq_error_handler(i2c_dev *dev) {
I2C_CRUMB(ERROR_ENTRY, dev->regs->SR1, dev->regs->SR2);
dev->error_flags = dev->regs->SR2 & (I2C_SR1_BERR |
I2C_SR1_ARLO |
I2C_SR1_AF |
I2C_SR1_OVR);
/* Clear flags */
dev->regs->SR1 = 0;
dev->regs->SR2 = 0;
i2c_stop_condition(dev);
i2c_disable_irq(dev, I2C_IRQ_BUFFER | I2C_IRQ_EVENT | I2C_IRQ_ERROR);
dev->state = I2C_STATE_ERROR;
}
void iic_test(void)
{
int i;
int ret;
unsigned char str[20];
for (i = 0; i < 20; i++) str[i] = 0x00;
i2c_init();
i2c_master_recv_data(SLAVE_ADDRS,
str, 10);
i2c_disable_irq();
for (i = 0; i < 10; i++) {
putc(str[i]);
}
}
/*
* IRQ handler for I2C master. Handles transmission/reception.
*/
void _i2c_irq_handler(i2c_dev *dev) {
/* WTFs:
* - Where is I2C_MSG_10BIT_ADDR handled?
*/
i2c_msg *msg = dev->msg;
uint8 read = msg->flags & I2C_MSG_READ;
uint32 sr1 = dev->regs->SR1;
uint32 sr2 = dev->regs->SR2;
I2C_CRUMB(IRQ_ENTRY, sr1, sr2);
/*
* Reset timeout counter
*/
dev->timestamp = systick_uptime();
/*
* Add Slave support
*/
/* Check to see if MSL master slave bit is set */
if ((sr2 & I2C_SR2_MSL) != I2C_SR2_MSL) { /* 0 = slave mode 1 = master */
/* Check for address match */
if (sr1 & I2C_SR1_ADDR) {
/* Find out which address was matched */
/* Check the general call address first */
if (sr2 & I2C_SR2_GENCALL) {
dev->i2c_slave_msg->addr = 0;
}
/* We matched the secondary address */
else if (sr2 & I2C_SR2_DUALF) {
dev->i2c_slave_msg->addr = dev->regs->OAR2 & 0xFE;
}
/* We matched the primary address */
else if ((sr2 & I2C_SR2_DUALF) != I2C_SR2_DUALF) {
dev->i2c_slave_msg->addr = dev->regs->OAR1 & 0xFE;
}
/* Shouldn't get here */
else {
dev->i2c_slave_msg->addr = -1; /* uh oh */
}
/* if we have buffered io */
if ((dev->config_flags & I2C_SLAVE_USE_RX_BUFFER) ||
(dev->config_flags & I2C_SLAVE_USE_TX_BUFFER)) {
/* if receiving then this would be a repeated start
*
*if we have some bytes already
*/
if ((dev->state == I2C_STATE_SL_RX) &&
(dev->i2c_slave_msg->xferred > 0) &&
(dev->config_flags & I2C_SLAVE_USE_RX_BUFFER)) {
/* Call the callback with the contents of the data */
if (dev->i2c_slave_recv_callback != NULL) {
(*(dev->i2c_slave_recv_callback))(dev->i2c_slave_msg);
}
}
/* Reset the message back to defaults.
* We are starting a new message
*/
dev->i2c_slave_msg->flags = 0;
dev->i2c_slave_msg->length = 0;
dev->i2c_slave_msg->xferred = 0;
dev->msgs_left = 0;
dev->timestamp = systick_uptime();
/* We have been addressed with SLA+R so
* the master wants us to transmit
*/
if ((sr1 & I2C_SR1_TXE) &&
(dev->config_flags & I2C_SLAVE_USE_TX_BUFFER)) {
/* Call the transmit callback so it can populate the msg
* data with the bytes to go
*/
if (dev->i2c_slave_transmit_callback != NULL) {
(*(dev->i2c_slave_transmit_callback))(dev->i2c_slave_msg);
}
}
dev->state = I2C_STATE_BUSY;
}
sr1 = sr2 = 0;
}
/* EV3: Master requesting data from slave. Transmit a byte*/
if (sr1 & I2C_SR1_TXE) {
if (dev->config_flags & I2C_SLAVE_USE_TX_BUFFER) {
if (dev->i2c_slave_msg->xferred >= dev->i2c_slave_msg->length) {
/* End of the transmit buffer? If so we NACK */
i2c_disable_ack(dev);
/* We have to either issue a STOP or write something here.
* STOP here seems to screw up some masters,
* For now padding with 0
*/
i2c_write(dev, 0);
/*i2c_stop_condition(dev); // This is causing bus lockups way more than it should !? Seems some I2C master devices freak out here*/
}
else
{
/* NACk the last byte */
if (dev->i2c_slave_msg->xferred == dev->i2c_slave_msg->length-1) {
i2c_disable_ack(dev);
}
else {
i2c_enable_ack(dev);
}
i2c_write(dev, dev->i2c_slave_msg->data[dev->i2c_slave_msg->xferred++]);
}
}
else
{
/* Call the callback to get the data we need.
* The callback is expected to write using i2c_write(...)
* If the slave is going to terminate the transfer, this function should
* also do a NACK on the last byte!
*/
if (dev->i2c_slave_transmit_callback != NULL) (*(dev->i2c_slave_transmit_callback))(dev->i2c_slave_msg);
}
dev->state = I2C_STATE_BUSY;
sr1 = sr2 = 0;
}
/* EV2: Slave received data from a master. Get from DR */
if (sr1 & I2C_SR1_RXNE) {
if (dev->config_flags & I2C_SLAVE_USE_RX_BUFFER) {
/* Fill the buffer with the contents of the data register */
/* These is potential for buffer overflow here, so we should
* really store the size of the array. This is expensive in
* the ISR so left out for now. We must trust the implementor!
*/
dev->i2c_slave_msg->data[dev->i2c_slave_msg->xferred++] = dev->regs->DR;
dev->i2c_slave_msg->length++;
}
else {
/* Call the callback with the contents of the data */
dev->i2c_slave_msg->data[0] = dev->regs->DR;
if (dev->i2c_slave_recv_callback != NULL) (*(dev->i2c_slave_recv_callback))(dev->i2c_slave_msg);
}
dev->state = I2C_STATE_SL_RX;
sr1 = sr2 = 0;
}
/* EV4: Slave has detected a STOP condition on the bus */
if (sr1 & I2C_SR1_STOPF) {
dev->regs->CR1 |= I2C_CR1_PE;
if ((dev->config_flags & I2C_SLAVE_USE_RX_BUFFER) ||
(dev->config_flags & I2C_SLAVE_USE_TX_BUFFER)) {
/* The callback with the data will happen on a NACK of the last data byte.
* This is handled in the error IRQ (AF bit)
*/
/* Handle the case where the master misbehaves by sending no NACK */
if (dev->state != I2C_STATE_IDLE) {
if (dev->state == I2C_STATE_SL_RX) {
if (dev->i2c_slave_recv_callback != NULL) (*(dev->i2c_slave_recv_callback))(dev->i2c_slave_msg);
}
else {
if (dev->i2c_slave_transmit_callback != NULL) (*(dev->i2c_slave_transmit_callback))(dev->i2c_slave_msg);
}
}
}
sr1 = sr2 = 0;
dev->state = I2C_STATE_IDLE;
}
return;
}
/*
* EV5: Start condition sent
*/
if (sr1 & I2C_SR1_SB) {
msg->xferred = 0;
i2c_enable_irq(dev, I2C_IRQ_BUFFER);
/*
* Master receiver
*/
if (read) {
i2c_enable_ack(dev);
}
i2c_send_slave_addr(dev, msg->addr, read);
sr1 = sr2 = 0;
}
/*
* EV6: Slave address sent
*/
if (sr1 & I2C_SR1_ADDR) {
/*
* Special case event EV6_1 for master receiver.
* Generate NACK and restart/stop condition after ADDR
* is cleared.
*/
if (read) {
if (msg->length == 1) {
i2c_disable_ack(dev);
if (dev->msgs_left > 1) {
i2c_start_condition(dev);
I2C_CRUMB(RX_ADDR_START, 0, 0);
} else {
i2c_stop_condition(dev);
I2C_CRUMB(RX_ADDR_STOP, 0, 0);
}
}
} else {
/*
* Master transmitter: write first byte to fill shift
* register. We should get another TXE interrupt
* immediately to fill DR again.
*/
if (msg->length != 1) {
i2c_write(dev, msg->data[msg->xferred++]);
}
}
sr1 = sr2 = 0;
}
/*
* EV8: Master transmitter
* Transmit buffer empty, but we haven't finished transmitting the last
* byte written.
*/
if ((sr1 & I2C_SR1_TXE) && !(sr1 & I2C_SR1_BTF)) {
I2C_CRUMB(TXE_ONLY, 0, 0);
if (dev->msgs_left) {
i2c_write(dev, msg->data[msg->xferred++]);
if (msg->xferred == msg->length) {
/*
* End of this message. Turn off TXE/RXNE and wait for
* BTF to send repeated start or stop condition.
*/
i2c_disable_irq(dev, I2C_IRQ_BUFFER);
dev->msgs_left--;
}
} else {
/*
* This should be impossible...
*/
ASSERT(0);
}
sr1 = sr2 = 0;
}
/*
* EV8_2: Master transmitter
* Last byte sent, program repeated start/stop
*/
if ((sr1 & I2C_SR1_TXE) && (sr1 & I2C_SR1_BTF)) {
I2C_CRUMB(TXE_BTF, 0, 0);
if (dev->msgs_left) {
I2C_CRUMB(TEST, 0, 0);
/*
* Repeated start insanity: We can't disable ITEVTEN or else SB
* won't interrupt, but if we don't disable ITEVTEN, BTF will
* continually interrupt us. What the f**k ST?
*/
i2c_start_condition(dev);
while (!(dev->regs->SR1 & I2C_SR1_SB))
;
dev->msg++;
} else {
i2c_stop_condition(dev);
/*
* Turn off event interrupts to keep BTF from firing until
* the end of the stop condition. Why on earth they didn't
* have a start/stop condition request clear BTF is beyond
* me.
*/
i2c_disable_irq(dev, I2C_IRQ_EVENT);
I2C_CRUMB(STOP_SENT, 0, 0);
dev->state = I2C_STATE_XFER_DONE;
}
sr1 = sr2 = 0;
}
/*
* EV7: Master Receiver
*/
if (sr1 & I2C_SR1_RXNE) {
I2C_CRUMB(RXNE_ONLY, 0, 0);
msg->data[msg->xferred++] = dev->regs->DR;
/*
* EV7_1: Second to last byte in the reception? Set NACK and generate
* stop/restart condition in time for the last byte. We'll get one more
* RXNE interrupt before shutting things down.
*/
if (msg->xferred == (msg->length - 1)) {
i2c_disable_ack(dev);
if (dev->msgs_left > 2) {
i2c_start_condition(dev);
I2C_CRUMB(RXNE_START_SENT, 0, 0);
} else {
i2c_stop_condition(dev);
I2C_CRUMB(RXNE_STOP_SENT, 0, 0);
}
} else if (msg->xferred == msg->length) {
dev->msgs_left--;
if (dev->msgs_left == 0) {
/*
* We're done.
*/
I2C_CRUMB(RXNE_DONE, 0, 0);
dev->state = I2C_STATE_XFER_DONE;
} else {
dev->msg++;
}
}
}
}
/**
* @brief IRQ handler for I2C master. Handles transmission/reception.
* @param dev I2C device
*/
static void i2c_irq_handler(i2c_dev *dev) {
i2c_msg *msg = dev->msg;
uint8 read = msg->flags & I2C_MSG_READ;
uint32 sr1 = dev->regs->SR1;
uint32 sr2 = dev->regs->SR2;
I2C_CRUMB(IRQ_ENTRY, sr1, sr2);
/*
* Reset timeout counter
*/
dev->timestamp = systick_uptime();
/*
* EV5: Start condition sent
*/
if (sr1 & I2C_SR1_SB) {
msg->xferred = 0;
i2c_enable_irq(dev, I2C_IRQ_BUFFER);
/*
* Master receiver
*/
if (read) {
i2c_enable_ack(dev);
}
i2c_send_slave_addr(dev, msg->addr, read);
sr1 = sr2 = 0;
}
/*
* EV6: Slave address sent
*/
if (sr1 & I2C_SR1_ADDR) {
/*
* Special case event EV6_1 for master receiver.
* Generate NACK and restart/stop condition after ADDR
* is cleared.
*/
if (read) {
if (msg->length == 1) {
i2c_disable_ack(dev);
if (dev->msgs_left > 1) {
i2c_start_condition(dev);
I2C_CRUMB(RX_ADDR_START, 0, 0);
} else {
i2c_stop_condition(dev);
I2C_CRUMB(RX_ADDR_STOP, 0, 0);
}
}
} else {
/*
* Master transmitter: write first byte to fill shift
* register. We should get another TXE interrupt
* immediately to fill DR again.
*/
if (msg->length != 1) {
i2c_write(dev, msg->data[msg->xferred++]);
}
}
sr1 = sr2 = 0;
}
/*
* EV8: Master transmitter
* Transmit buffer empty, but we haven't finished transmitting the last
* byte written.
*/
if ((sr1 & I2C_SR1_TXE) && !(sr1 & I2C_SR1_BTF)) {
I2C_CRUMB(TXE_ONLY, 0, 0);
if (dev->msgs_left) {
i2c_write(dev, msg->data[msg->xferred++]);
if (msg->xferred == msg->length) {
/*
* End of this message. Turn off TXE/RXNE and wait for
* BTF to send repeated start or stop condition.
*/
i2c_disable_irq(dev, I2C_IRQ_BUFFER);
dev->msgs_left--;
}
} else {
/*
* This should be impossible...
*/
throb();
}
sr1 = sr2 = 0;
}
/*
* EV8_2: Master transmitter
* Last byte sent, program repeated start/stop
*/
if ((sr1 & I2C_SR1_TXE) && (sr1 & I2C_SR1_BTF)) {
I2C_CRUMB(TXE_BTF, 0, 0);
if (dev->msgs_left) {
I2C_CRUMB(TEST, 0, 0);
/*
* Repeated start insanity: We can't disable ITEVTEN or else SB
* won't interrupt, but if we don't disable ITEVTEN, BTF will
* continually interrupt us. What the f**k ST?
*/
i2c_start_condition(dev);
while (!(dev->regs->SR1 & I2C_SR1_SB))
;
dev->msg++;
} else {
i2c_stop_condition(dev);
/*
* Turn off event interrupts to keep BTF from firing until
* the end of the stop condition. Why on earth they didn't
* have a start/stop condition request clear BTF is beyond
* me.
*/
i2c_disable_irq(dev, I2C_IRQ_EVENT);
I2C_CRUMB(STOP_SENT, 0, 0);
dev->state = I2C_STATE_XFER_DONE;
}
sr1 = sr2 = 0;
}
/*
* EV7: Master Receiver
*/
if (sr1 & I2C_SR1_RXNE) {
I2C_CRUMB(RXNE_ONLY, 0, 0);
msg->data[msg->xferred++] = dev->regs->DR;
/*
* EV7_1: Second to last byte in the reception? Set NACK and generate
* stop/restart condition in time for the last byte. We'll get one more
* RXNE interrupt before shutting things down.
*/
if (msg->xferred == (msg->length - 1)) {
i2c_disable_ack(dev);
if (dev->msgs_left > 2) {
i2c_start_condition(dev);
I2C_CRUMB(RXNE_START_SENT, 0, 0);
} else {
i2c_stop_condition(dev);
I2C_CRUMB(RXNE_STOP_SENT, 0, 0);
}
} else if (msg->xferred == msg->length) {
dev->msgs_left--;
if (dev->msgs_left == 0) {
/*
* We're done.
*/
I2C_CRUMB(RXNE_DONE, 0, 0);
dev->state = I2C_STATE_XFER_DONE;
} else {
dev->msg++;
}
}
}
}
