コード例 #1
0
static int __init hugetlb_setup_sz(char *str)
{
	u64 tr_pages;
	unsigned long long size;

	if (ia64_pal_vm_page_size(&tr_pages, NULL) != 0)
		/*
		 * shouldn't happen, but just in case.
		 */
		tr_pages = 0x15557000UL;

	size = memparse(str, &str);
	if (*str || !is_power_of_2(size) || !(tr_pages & size) ||
		size <= PAGE_SIZE ||
		size >= (1UL << PAGE_SHIFT << MAX_ORDER)) {
		printk(KERN_WARNING "Invalid huge page size specified\n");
		return 1;
	}

	hpage_shift = __ffs(size);
	/*
	 * boot cpu already executed ia64_mmu_init, and has HPAGE_SHIFT_DEFAULT
	 * override here with new page shift.
	 */
	ia64_set_rr(HPAGE_REGION_BASE, hpage_shift << 2);
	return 0;
}
コード例 #2
0
ファイル: tlb.c プロジェクト: sarnobat/knoppix
void __init
ia64_tlb_init (void)
{
	ia64_ptce_info_t ptce_info;
	unsigned long tr_pgbits;
	long status;

	if ((status = ia64_pal_vm_page_size(&tr_pgbits, &purge.mask)) != 0) {
		printk(KERN_ERR "PAL_VM_PAGE_SIZE failed with status=%ld;"
		       "defaulting to architected purge page-sizes.\n", status);
		purge.mask = 0x115557000;
	}
	purge.max_bits = ia64_fls(purge.mask);

	ia64_get_ptce(&ptce_info);
	local_cpu_data->ptce_base = ptce_info.base;
	local_cpu_data->ptce_count[0] = ptce_info.count[0];
	local_cpu_data->ptce_count[1] = ptce_info.count[1];
	local_cpu_data->ptce_stride[0] = ptce_info.stride[0];
	local_cpu_data->ptce_stride[1] = ptce_info.stride[1];

	local_flush_tlb_all();		/* nuke left overs from bootstrapping... */
}
コード例 #3
0
static int
vm_info(char *page)
{
	char *p = page;
	u64 tr_pages =0, vw_pages=0, tc_pages;
	u64 attrib;
	pal_vm_info_1_u_t vm_info_1;
	pal_vm_info_2_u_t vm_info_2;
	pal_tc_info_u_t	tc_info;
	ia64_ptce_info_t ptce;
	const char *sep;
	int i, j;
	long status;

	if ((status = ia64_pal_vm_summary(&vm_info_1, &vm_info_2)) !=0) {
		printk(KERN_ERR "ia64_pal_vm_summary=%ld\n", status);
	} else {

		p += sprintf(p,
		     "Physical Address Space         : %d bits\n"
		     "Virtual Address Space          : %d bits\n"
		     "Protection Key Registers(PKR)  : %d\n"
		     "Implemented bits in PKR.key    : %d\n"
		     "Hash Tag ID                    : 0x%x\n"
		     "Size of RR.rid                 : %d\n"
		     "Max Purges                     : ",
		     vm_info_1.pal_vm_info_1_s.phys_add_size,
		     vm_info_2.pal_vm_info_2_s.impl_va_msb+1,
		     vm_info_1.pal_vm_info_1_s.max_pkr+1,
		     vm_info_1.pal_vm_info_1_s.key_size,
		     vm_info_1.pal_vm_info_1_s.hash_tag_id,
		     vm_info_2.pal_vm_info_2_s.rid_size);
		if (vm_info_2.pal_vm_info_2_s.max_purges == PAL_MAX_PURGES)
			p += sprintf(p, "unlimited\n");
		else
			p += sprintf(p, "%d\n",
		     		vm_info_2.pal_vm_info_2_s.max_purges ?
				vm_info_2.pal_vm_info_2_s.max_purges : 1);
	}

	if (ia64_pal_mem_attrib(&attrib) == 0) {
		p += sprintf(p, "Supported memory attributes    : ");
		sep = "";
		for (i = 0; i < 8; i++) {
			if (attrib & (1 << i)) {
				p += sprintf(p, "%s%s", sep, mem_attrib[i]);
				sep = ", ";
			}
		}
		p += sprintf(p, "\n");
	}

	if ((status = ia64_pal_vm_page_size(&tr_pages, &vw_pages)) !=0) {
		printk(KERN_ERR "ia64_pal_vm_page_size=%ld\n", status);
	} else {

		p += sprintf(p,
			     "\nTLB walker                     : %simplemented\n"
			     "Number of DTR                  : %d\n"
			     "Number of ITR                  : %d\n"
			     "TLB insertable page sizes      : ",
			     vm_info_1.pal_vm_info_1_s.vw ? "" : "not ",
			     vm_info_1.pal_vm_info_1_s.max_dtr_entry+1,
			     vm_info_1.pal_vm_info_1_s.max_itr_entry+1);


		p = bitvector_process(p, tr_pages);

		p += sprintf(p, "\nTLB purgeable page sizes       : ");

		p = bitvector_process(p, vw_pages);
	}
	if ((status=ia64_get_ptce(&ptce)) != 0) {
		printk(KERN_ERR "ia64_get_ptce=%ld\n", status);
	} else {
		p += sprintf(p,
		     "\nPurge base address             : 0x%016lx\n"
		     "Purge outer loop count         : %d\n"
		     "Purge inner loop count         : %d\n"
		     "Purge outer loop stride        : %d\n"
		     "Purge inner loop stride        : %d\n",
		     ptce.base, ptce.count[0], ptce.count[1],
		     ptce.stride[0], ptce.stride[1]);

		p += sprintf(p,
		     "TC Levels                      : %d\n"
		     "Unique TC(s)                   : %d\n",
		     vm_info_1.pal_vm_info_1_s.num_tc_levels,
		     vm_info_1.pal_vm_info_1_s.max_unique_tcs);

		for(i=0; i < vm_info_1.pal_vm_info_1_s.num_tc_levels; i++) {
			for (j=2; j>0 ; j--) {
				tc_pages = 0; /* just in case */


				/* even without unification, some levels may not be present */
				if ((status=ia64_pal_vm_info(i,j, &tc_info, &tc_pages)) != 0) {
					continue;
				}

				p += sprintf(p,
				     "\n%s Translation Cache Level %d:\n"
				     "\tHash sets           : %d\n"
				     "\tAssociativity       : %d\n"
				     "\tNumber of entries   : %d\n"
				     "\tFlags               : ",
				     cache_types[j+tc_info.tc_unified], i+1,
				     tc_info.tc_num_sets,
				     tc_info.tc_associativity,
				     tc_info.tc_num_entries);

				if (tc_info.tc_pf)
					p += sprintf(p, "PreferredPageSizeOptimized ");
				if (tc_info.tc_unified)
					p += sprintf(p, "Unified ");
				if (tc_info.tc_reduce_tr)
					p += sprintf(p, "TCReduction");

				p += sprintf(p, "\n\tSupported page sizes: ");

				p = bitvector_process(p, tc_pages);

				/* when unified date (j=2) is enough */
				if (tc_info.tc_unified)
					break;
			}
		}
	}
	p += sprintf(p, "\n");

	return p - page;
}