static void proc_reports_siimage (struct pci_dev *dev, u8 clocking, const char *name)
{
if(pdev_is_sata(dev))
goto sata_skip;
printk(KERN_INFO "%s: BASE CLOCK ", name);
clocking &= 0x03;
switch(clocking) {
case 0x03: printk("DISABLED !\n"); break;
case 0x02: printk("== 2X PCI \n"); break;
case 0x01: printk("== 133 \n"); break;
case 0x00: printk("== 100 \n"); break;
}
sata_skip:
#if defined(DISPLAY_SIIMAGE_TIMINGS) && defined(CONFIG_PROC_FS)
siimage_devs[n_siimage_devs++] = dev;
if (!siimage_proc) {
siimage_proc = 1;
ide_pci_register_host_proc(&siimage_procs[0]);
}
#endif /* DISPLAY_SIIMAGE_TIMINGS && CONFIG_PROC_FS */
}
static unsigned int __init
pci_init_sgiioc4(struct pci_dev *dev, const char *name)
{
if (pci_enable_device(dev)) {
printk(KERN_INFO "Failed to enable device %s at slot %s \n",name,dev->slot_name);
return 1;
}
pci_set_master(dev);
/* Enable Byte Swapping in the PIC... */
if (snia_pciio_endian_set) {
/* ... if the symbol exists (hack to get this to build
* for SuSE before we merge the SN2 code */
snia_pciio_endian_set(dev, PCIDMA_ENDIAN_LITTLE, PCIDMA_ENDIAN_BIG);
} else {
printk(KERN_INFO "Failed to set endianness for device %s at slot %s \n", name, dev->slot_name);
return 1;
}
#ifdef CONFIG_PROC_FS
sgiioc4_devs[n_sgiioc4_devs++] = dev;
if (!sgiioc4_proc) {
sgiioc4_proc = 1;
ide_pci_register_host_proc(&sgiioc4_procs[0]);
}
#endif
sgiioc4_ide_setup_pci_device(dev, name);
return 0;
}
static unsigned int __init init_chipset_slc90e66 (struct pci_dev *dev, const char *name)
{
#if defined(DISPLAY_SLC90E66_TIMINGS) && defined(CONFIG_PROC_FS)
if (!slc90e66_proc) {
slc90e66_proc = 1;
bmide_dev = dev;
ide_pci_register_host_proc(&slc90e66_procs[0]);
}
#endif /* DISPLAY_SLC90E66_TIMINGS && CONFIG_PROC_FS */
return 0;
}
static unsigned int __devinit init_chipset_piix (struct pci_dev *dev, const char *name)
{
switch(dev->device) {
case PCI_DEVICE_ID_INTEL_82801EB_1:
case PCI_DEVICE_ID_INTEL_82801AA_1:
case PCI_DEVICE_ID_INTEL_82801AB_1:
case PCI_DEVICE_ID_INTEL_82801BA_8:
case PCI_DEVICE_ID_INTEL_82801BA_9:
case PCI_DEVICE_ID_INTEL_82801CA_10:
case PCI_DEVICE_ID_INTEL_82801CA_11:
case PCI_DEVICE_ID_INTEL_82801DB_1:
case PCI_DEVICE_ID_INTEL_82801DB_10:
case PCI_DEVICE_ID_INTEL_82801DB_11:
case PCI_DEVICE_ID_INTEL_82801EB_11:
case PCI_DEVICE_ID_INTEL_82801E_11:
case PCI_DEVICE_ID_INTEL_ESB_2:
case PCI_DEVICE_ID_INTEL_ICH6_19:
case PCI_DEVICE_ID_INTEL_ICH7_21:
case PCI_DEVICE_ID_INTEL_ESB2_18:
{
unsigned int extra = 0;
pci_read_config_dword(dev, 0x54, &extra);
pci_write_config_dword(dev, 0x54, extra|0x400);
}
default:
break;
}
#if defined(DISPLAY_PIIX_TIMINGS) && defined(CONFIG_PROC_FS)
piix_devs[n_piix_devs++] = dev;
if (!piix_proc) {
piix_proc = 1;
ide_pci_register_host_proc(&piix_procs[0]);
}
#endif /* DISPLAY_PIIX_TIMINGS && CONFIG_PROC_FS */
return 0;
}
static unsigned int __init init_chipset_cmd64x (struct pci_dev *dev, const char *name)
{
u32 class_rev = 0;
u8 mrdmode = 0;
pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
class_rev &= 0xff;
#ifdef __i386__
if (dev->resource[PCI_ROM_RESOURCE].start) {
pci_write_config_byte(dev, PCI_ROM_ADDRESS, dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n", name, dev->resource[PCI_ROM_RESOURCE].start);
}
#endif
switch(dev->device) {
case PCI_DEVICE_ID_CMD_643:
break;
case PCI_DEVICE_ID_CMD_646:
printk(KERN_INFO "%s: chipset revision 0x%02X, ", name, class_rev);
switch(class_rev) {
case 0x07:
case 0x05:
printk("UltraDMA Capable");
break;
case 0x03:
printk("MultiWord DMA Force Limited");
break;
case 0x01:
default:
printk("MultiWord DMA Limited, IRQ workaround enabled");
break;
}
printk("\n");
break;
case PCI_DEVICE_ID_CMD_648:
case PCI_DEVICE_ID_CMD_649:
break;
default:
break;
}
/* Set a good latency timer and cache line size value. */
(void) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
#ifdef __sparc_v9__
(void) pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x10);
#endif
/* Setup interrupts. */
(void) pci_read_config_byte(dev, MRDMODE, &mrdmode);
mrdmode &= ~(0x30);
(void) pci_write_config_byte(dev, MRDMODE, mrdmode);
/* Use MEMORY READ LINE for reads.
* NOTE: Although not mentioned in the PCI0646U specs,
* these bits are write only and won't be read
* back as set or not. The PCI0646U2 specs clarify
* this point.
*/
(void) pci_write_config_byte(dev, MRDMODE, mrdmode | 0x02);
/* Set reasonable active/recovery/address-setup values. */
(void) pci_write_config_byte(dev, ARTTIM0, 0x40);
(void) pci_write_config_byte(dev, DRWTIM0, 0x3f);
(void) pci_write_config_byte(dev, ARTTIM1, 0x40);
(void) pci_write_config_byte(dev, DRWTIM1, 0x3f);
#ifdef __i386__
(void) pci_write_config_byte(dev, ARTTIM23, 0x1c);
#else
(void) pci_write_config_byte(dev, ARTTIM23, 0x5c);
#endif
(void) pci_write_config_byte(dev, DRWTIM23, 0x3f);
(void) pci_write_config_byte(dev, DRWTIM3, 0x3f);
#ifdef CONFIG_PPC
(void) pci_write_config_byte(dev, UDIDETCR0, 0xf0);
#endif /* CONFIG_PPC */
#if defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_PROC_FS)
cmd_devs[n_cmd_devs++] = dev;
if (!cmd64x_proc) {
cmd64x_proc = 1;
ide_pci_register_host_proc(&cmd64x_procs[0]);
}
#endif /* DISPLAY_CMD64X_TIMINGS && CONFIG_PROC_FS */
return 0;
}
static unsigned int __init init_chipset_aec62xx (struct pci_dev *dev, const char *name)
{
int bus_speed = system_bus_clock();
#ifndef CONFIG_BCM947XX
if (dev->resource[PCI_ROM_RESOURCE].start) {
pci_write_config_dword(dev, PCI_ROM_ADDRESS, dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n", name, dev->resource[PCI_ROM_RESOURCE].start);
}
#else
if (dev->resource[PCI_ROM_RESOURCE].start) {
pci_write_config_dword(dev, PCI_ROM_ADDRESS,
dev->resource[PCI_ROM_RESOURCE].
start | PCI_ROM_ADDRESS_ENABLE);
} else {
pci_write_config_dword(dev, PCI_ROM_ADDRESS,
dev->resource[PCI_ROM_RESOURCE].
start);
}
/* Set IDE controller parameters manually - FIXME: replace magic values */
{
byte setting;
pci_write_config_word(dev, PCI_COMMAND, 0x0007);
//pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x5A);
pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x13);
pci_write_config_byte(dev, 0x40, 0x31);
pci_write_config_byte(dev, 0x41, 0x31);
pci_write_config_byte(dev, 0x42, 0x31);
pci_write_config_byte(dev, 0x43, 0x31);
// Set IDE Command Speed
pci_write_config_byte(dev, 0x48, 0x31);
// Disable WriteSubSysID & PIOROM
pci_read_config_byte(dev, 0x49, &setting);
setting &= 0x07;
pci_write_config_byte(dev, 0x49, setting);
// Enable PCI burst & INTA & PCI memory read multiple, FIFO threshold=80
pci_read_config_byte(dev, 0x4A, &setting);
//setting = (setting & 0xFE) | 0xA8;
setting = (setting & 0xFE) | 0xD8;
setting = (setting & 0xF7);
pci_write_config_byte(dev, 0x4A, setting);
//pci_write_config_byte(dev, 0x4B, 0x20);
pci_write_config_byte(dev, 0x4B, 0x2C);
//pci_write_config_byte(dev, 0x4B, 0x0C);
// Set PreRead count: 512 byte
pci_write_config_byte(dev, 0x4C, 0);
pci_write_config_word(dev, 0x4D, 0x0002);
pci_write_config_byte(dev, 0x54, 0);
pci_write_config_word(dev, 0x55, 0x0002);
}
#endif
#if defined(DISPLAY_AEC62XX_TIMINGS) && defined(CONFIG_PROC_FS)
aec_devs[n_aec_devs++] = dev;
if (!aec62xx_proc) {
aec62xx_proc = 1;
ide_pci_register_host_proc(&aec62xx_procs[0]);
}
#endif /* DISPLAY_AEC62XX_TIMINGS && CONFIG_PROC_FS */
if (bus_speed <= 33)
pci_set_drvdata(dev, (void *) aec6xxx_33_base);
else
pci_set_drvdata(dev, (void *) aec6xxx_34_base);
return dev->irq;
}
