static int imx1_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
unsigned group)
{
struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx1_pinctrl_soc_info *info = ipctl->info;
const struct imx1_pin *pins;
unsigned int npins;
int i;
/*
* Configure the mux mode for each pin in the group for a specific
* function.
*/
pins = info->groups[group].pins;
npins = info->groups[group].npins;
WARN_ON(!pins || !npins);
dev_dbg(ipctl->dev, "enable function %s group %s\n",
info->functions[selector].name, info->groups[group].name);
for (i = 0; i < npins; i++) {
unsigned int mux = pins[i].mux_id;
unsigned int pin_id = pins[i].pin_id;
unsigned int afunction = MX1_MUX_FUNCTION(mux);
unsigned int gpio_in_use = MX1_MUX_GPIO(mux);
unsigned int direction = MX1_MUX_DIR(mux);
unsigned int gpio_oconf = MX1_MUX_OCONF(mux);
unsigned int gpio_iconfa = MX1_MUX_ICONFA(mux);
unsigned int gpio_iconfb = MX1_MUX_ICONFB(mux);
dev_dbg(pctldev->dev, "%s, pin 0x%x, function %d, gpio %d, direction %d, oconf %d, iconfa %d, iconfb %d\n",
__func__, pin_id, afunction, gpio_in_use,
direction, gpio_oconf, gpio_iconfa,
gpio_iconfb);
imx1_write_bit(ipctl, pin_id, gpio_in_use, MX1_GIUS);
imx1_write_bit(ipctl, pin_id, direction, MX1_DDIR);
if (gpio_in_use) {
imx1_write_2bit(ipctl, pin_id, gpio_oconf, MX1_OCR);
imx1_write_2bit(ipctl, pin_id, gpio_iconfa,
MX1_ICONFA);
imx1_write_2bit(ipctl, pin_id, gpio_iconfb,
MX1_ICONFB);
} else {
imx1_write_bit(ipctl, pin_id, afunction, MX1_GPR);
}
}
return 0;
}
static int imx1_pinconf_set(struct pinctrl_dev *pctldev,
unsigned pin_id, unsigned long *configs,
unsigned num_configs)
{
struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
int i;
for (i = 0; i != num_configs; ++i) {
imx1_write_bit(ipctl, pin_id, configs[i] & 0x01, MX1_PUEN);
dev_dbg(ipctl->dev, "pinconf set pullup pin %s\n",
pin_desc_get(pctldev, pin_id)->name);
}
return 0;
}
