static u32 imx_write(struct vmm_chardev *cdev,
u8 *src, size_t len, off_t __unused *off, bool sleep)
{
u32 i;
struct imx_port *port;
if (!(cdev && src && cdev->priv)) {
return 0;
}
port = cdev->priv;
#if defined(UART_IMX_USE_TXINTR)
if (sleep) {
for (i = 0; i < len; i++) {
imx_putc_sleepable(port, src[i]);
}
} else {
for (i = 0; i < len; i++) {
if (!imx_lowlevel_can_putc(port->base)) {
break;
}
imx_lowlevel_putc(port->base, src[i]);
}
}
#else
for (i = 0; i < len; i++) {
if (!imx_lowlevel_can_putc(port->base)) {
break;
}
imx_lowlevel_putc(port->base, src[i]);
}
#endif
return i;
}
static int imx_defterm_putc(u8 ch)
{
if (!imx_lowlevel_can_putc(imx_defterm_base)) {
return VMM_EFAIL;
}
imx_lowlevel_putc(imx_defterm_base, ch);
return VMM_OK;
}
static void imx_putc_sleepable(struct imx_port *port, u8 ch)
{
/* Wait until there is space in the FIFO */
if (!imx_lowlevel_can_putc(port->base)) {
/* Enable the RX interrupt */
port->mask |= UCR1_TRDYEN;
vmm_writel(port->mask, (void *)port->base + UCR1);
/* Wait for completion */
vmm_completion_wait(&port->write_possible);
}
/* Write data to FIFO */
imx_lowlevel_putc(port->base, ch);
}
static u32 imx_tx(struct serial *p, u8 *src, size_t len)
{
u32 i;
struct imx_port *port = serial_tx_priv(p);
for (i = 0; i < len; i++) {
if (!imx_lowlevel_can_putc(port->base)) {
break;
}
imx_lowlevel_putc(port->base, src[i]);
}
return i;
}
