/*
* cpu irq handler
*/
void __init nxp_cpu_init_irq(void)
{
pr_debug("%s\n", __func__);
nxp_cpu_vic_priority();
nxp_cpu_vic_table();
#ifndef CONFIG_ARM_GIC
/* VIC to core */
writel_relaxed(0, GIC_CPUI_BASE);
#endif
vic_init (VIC0_INT_BASE , 0, VIC0_INT_MASK, VIC0_INT_RESUME); /* 0 ~ 31 */
vic_init (VIC1_INT_BASE , 32, VIC1_INT_MASK, VIC1_INT_RESUME); /* 32 ~ 59 */
gpio_init (GPIO_INT_BASE , IRQ_GPIO_START, GPIO_INT_MASK, 0); /* 64 ~ 223 (A,B,C,D,E) */
alive_init(ALIVE_INT_BASE, IRQ_ALIVE_START, ALIVE_INT_MASK, 0); /* 224 ~ 231 */
#ifdef CONFIG_ARM_GIC
__gic_init(GIC_DIST_BASE, (void __iomem *)GIC_CPUI_BASE);
#endif
#ifdef CONFIG_FIQ
init_FIQ();
#endif
__vic_set_irq_chip();
/* wake up source from idle */
irq_set_irq_wake(IRQ_PHY_CLKPWR_ALIVEIRQ, 1);
#if PM_RTC_WAKE
irq_set_irq_wake(IRQ_PHY_CLKPWR_RTCIRQ, 1);
#endif
}
void __init lh7a40x_init_board_irq (void)
{
int irq;
for (irq = IRQ_KEV7A400_CPLD;
irq < IRQ_KEV7A400_CPLD + NR_IRQ_BOARD; ++irq) {
set_irq_chip (irq, &kev7a400_cpld_chip);
set_irq_handler (irq, handle_edge_irq);
set_irq_flags (irq, IRQF_VALID);
}
set_irq_chained_handler (IRQ_CPLD, kev7a400_cpld_handler);
/* Clear all CPLD interrupts */
CPLD_CL_INT = 0xff; /* CPLD_INTR_MMC_CD | CPLD_INTR_ETH_INT; */
GPIO_GPIOINTEN = 0; /* Disable all GPIO interrupts */
barrier();
#if 0
GPIO_INTTYPE1
= (GPIO_INTR_PCC1_CD | GPIO_INTR_PCC1_CD); /* Edge trig. */
GPIO_INTTYPE2 = 0; /* Falling edge & low-level */
GPIO_GPIOFEOI = 0xff; /* Clear all GPIO interrupts */
GPIO_GPIOINTEN = 0xff; /* Enable all GPIO interrupts */
init_FIQ();
#endif
}
void __init rpc_init_irq(void)
{
unsigned int irq, clr, set = 0;
iomd_writeb(0, IOMD_IRQMASKA);
iomd_writeb(0, IOMD_IRQMASKB);
iomd_writeb(0, IOMD_FIQMASK);
iomd_writeb(0, IOMD_DMAMASK);
set_fiq_handler(&rpc_default_fiq_start,
&rpc_default_fiq_end - &rpc_default_fiq_start);
for (irq = 0; irq < NR_IRQS; irq++) {
clr = IRQ_NOREQUEST;
if (irq <= 6 || (irq >= 9 && irq <= 15))
clr |= IRQ_NOPROBE;
if (irq == 21 || (irq >= 16 && irq <= 19) ||
irq == IRQ_KEYBOARDTX)
set |= IRQ_NOAUTOEN;
switch (irq) {
case 0 ... 7:
irq_set_chip_and_handler(irq, &iomd_a_chip,
handle_level_irq);
irq_modify_status(irq, clr, set);
break;
case 8 ... 15:
irq_set_chip_and_handler(irq, &iomd_b_chip,
handle_level_irq);
irq_modify_status(irq, clr, set);
break;
case 16 ... 21:
irq_set_chip_and_handler(irq, &iomd_dma_chip,
handle_level_irq);
irq_modify_status(irq, clr, set);
break;
case 64 ... 71:
irq_set_chip(irq, &iomd_fiq_chip);
irq_modify_status(irq, clr, set);
break;
}
}
init_FIQ(FIQ_START);
}
static void __init l7200_init_irq(void)
{
int irq;
IRQ_ENABLECLEAR = 0xffffffff; /* clear all interrupt enables */
FIQ_ENABLECLEAR = 0xffffffff; /* clear all fast interrupt enables */
for (irq = 0; irq < NR_IRQS; irq++) {
set_irq_chip(irq, &l7200_irq_chip);
set_irq_flags(irq, IRQF_VALID);
set_irq_handler(irq, handle_level_irq);
}
init_FIQ();
}
void __init rpc_init_irq(void)
{
unsigned int irq, flags;
iomd_writeb(0, IOMD_IRQMASKA);
iomd_writeb(0, IOMD_IRQMASKB);
iomd_writeb(0, IOMD_FIQMASK);
iomd_writeb(0, IOMD_DMAMASK);
for (irq = 0; irq < NR_IRQS; irq++) {
flags = IRQF_VALID;
if (irq <= 6 || (irq >= 9 && irq <= 15))
flags |= IRQF_PROBE;
if (irq == 21 || (irq >= 16 && irq <= 19) ||
irq == IRQ_KEYBOARDTX)
flags |= IRQF_NOAUTOEN;
switch (irq) {
case 0 ... 7:
irq_set_chip_and_handler(irq, &iomd_a_chip,
handle_level_irq);
set_irq_flags(irq, flags);
break;
case 8 ... 15:
irq_set_chip_and_handler(irq, &iomd_b_chip,
handle_level_irq);
set_irq_flags(irq, flags);
break;
case 16 ... 21:
irq_set_chip_and_handler(irq, &iomd_dma_chip,
handle_level_irq);
set_irq_flags(irq, flags);
break;
case 64 ... 71:
irq_set_chip(irq, &iomd_fiq_chip);
set_irq_flags(irq, IRQF_VALID);
break;
}
}
init_FIQ();
}
void __init s3c2410_init_irq(void)
{
#ifdef CONFIG_FIQ
init_FIQ(FIQ_START);
#endif
s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2410base[0], NULL,
0x4a000000);
if (IS_ERR(s3c_intc[0])) {
pr_err("irq: could not create main interrupt controller\n");
return;
}
s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2410subint[0],
s3c_intc[0], 0x4a000018);
s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
}
static void __init l7200_init_irq(void)
{
int irq;
IRQ_ENABLECLEAR = 0xffffffff; /* clear all interrupt enables */
FIQ_ENABLECLEAR = 0xffffffff; /* clear all fast interrupt enables */
for (irq = 0; irq < NR_IRQS; irq++) {
irq_desc[irq].valid = 1;
irq_desc[irq].probe_ok = 1;
irq_desc[irq].mask_ack = l7200_mask_irq;
irq_desc[irq].mask = l7200_mask_irq;
irq_desc[irq].unmask = l7200_unmask_irq;
}
init_FIQ();
}
static int __init armctrl_of_init(struct device_node *node,
struct device_node *parent)
{
void __iomem *base;
int irq, b, i;
base = of_iomap(node, 0);
if (!base)
panic("%s: unable to map IC registers\n",
node->full_name);
intc.base = base;
intc.domain = irq_domain_add_linear(node, NUMBER_IRQS * 2,
&armctrl_ops, NULL);
if (!intc.domain)
panic("%s: unable to create IRQ domain\n", node->full_name);
for (b = 0; b < NR_BANKS; b++) {
intc.pending[b] = base + reg_pending[b];
intc.enable[b] = base + reg_enable[b];
intc.disable[b] = base + reg_disable[b];
for (i = 0; i < bank_irqs[b]; i++) {
irq = irq_create_mapping(intc.domain, MAKE_HWIRQ(b, i));
BUG_ON(irq <= 0);
irq_set_chip_and_handler(irq, &armctrl_chip,
handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
}
set_handle_irq(bcm2835_handle_irq);
/* Make a duplicate irq range which is used to enable FIQ */
for (b = 0; b < NR_BANKS; b++) {
for (i = 0; i < bank_irqs[b]; i++) {
irq = irq_create_mapping(intc.domain,
MAKE_HWIRQ(b, i) + NUMBER_IRQS);
BUG_ON(irq <= 0);
irq_set_chip(irq, &armctrl_chip);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
}
init_FIQ(FIQ_START);
return 0;
}
/*
* cpu irq handler
*/
void __init nxp_cpu_irq_init(void)
{
pr_debug("%s:%d\n", __func__, __LINE__);
__gic_init(GIC_DIST_BASE, (void __iomem *)GIC_CPUI_BASE);
gpio_init(GPIO_INT_BASE , IRQ_GPIO_START, GPIO_INT_MASK, 0); /* 64 ~ 223 (A,B,C,D,E) */
alive_init(ALIVE_INT_BASE, IRQ_ALIVE_START, ALIVE_INT_MASK, 0); /* 224 ~ 231 */
#ifdef CONFIG_FIQ
init_FIQ();
#endif
/* wake up source from idle */
irq_set_irq_wake(IRQ_PHY_CLKPWR_ALIVEIRQ + GIC_PHY_OFFSET, 1);
#if PM_RTC_WAKE
irq_set_irq_wake(IRQ_PHY_CLKPWR_RTCIRQ + GIC_PHY_OFFSET, 1);
#endif
}
void __init
imx_init_irq(void)
{
unsigned int irq;
DEBUG_IRQ("Initializing imx interrupts\n");
/* Disable all interrupts initially. */
/* Do not rely on the bootloader. */
__raw_writel(0, IMX_AITC_INTENABLEH);
__raw_writel(0, IMX_AITC_INTENABLEL);
/* Mask all GPIO interrupts as well */
IMR(0) = 0;
IMR(1) = 0;
IMR(2) = 0;
IMR(3) = 0;
for (irq = 0; irq < IMX_IRQS; irq++) {
set_irq_chip(irq, &imx_internal_chip);
set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
}
for (irq = IRQ_GPIOA(0); irq < IRQ_GPIOD(32); irq++) {
set_irq_chip(irq, &imx_gpio_chip);
set_irq_handler(irq, handle_edge_irq);
set_irq_flags(irq, IRQF_VALID);
}
set_irq_chained_handler(GPIO_INT_PORTA, imx_gpioa_demux_handler);
set_irq_chained_handler(GPIO_INT_PORTB, imx_gpiob_demux_handler);
set_irq_chained_handler(GPIO_INT_PORTC, imx_gpioc_demux_handler);
set_irq_chained_handler(GPIO_INT_PORTD, imx_gpiod_demux_handler);
/* Release masking of interrupts according to priority */
__raw_writel(-1, IMX_AITC_NIMASK);
#ifdef CONFIG_FIQ
/* Initialize FIQ */
init_FIQ();
#endif
}
/*
* This function initializes the AVIC hardware and disables all the
* interrupts. It registers the interrupt enable and disable functions
* to the kernel for each interrupt source.
*/
void __init mxc_init_irq(void)
{
int i;
avic_base = IO_ADDRESS(AVIC_BASE_ADDR);
/* put the AVIC into the reset value with
* all interrupts disabled
*/
__raw_writel(0, avic_base + AVIC_INTCNTL);
__raw_writel(0x1f, avic_base + AVIC_NIMASK);
/* disable all interrupts */
__raw_writel(0, avic_base + AVIC_INTENABLEH);
__raw_writel(0, avic_base + AVIC_INTENABLEL);
/* all IRQ no FIQ */
__raw_writel(0, avic_base + AVIC_INTTYPEH);
__raw_writel(0, avic_base + AVIC_INTTYPEL);
for (i = 0; i < MXC_INTERNAL_IRQS; i++) {
set_irq_chip(i, &mxc_avic_chip);
set_irq_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID);
}
/* Set default priority value (0) for all IRQ's */
for (i = 0; i < 8; i++)
__raw_writel(0, avic_base + AVIC_NIPRIORITY(i));
#ifdef CONFIG_FIQ
/* Initialize FIQ */
init_FIQ();
#endif
if (MXC_INT_FORCE >= 32)
__raw_writel(1 << (MXC_INT_FORCE & 31), avic_base + AVIC_INTFRCH);
else if (MXC_INT_FORCE >= 0)
__raw_writel(1 << MXC_INT_FORCE, avic_base + AVIC_INTFRCL);
printk(KERN_INFO "MXC IRQ initialized\n");
}
/**
* armctrl_init - initialise a vectored interrupt controller
* @base: iomem base address
* @irq_start: starting interrupt number, must be muliple of 32
* @armctrl_sources: bitmask of interrupt sources to allow
* @resume_sources: bitmask of interrupt sources to allow for resume
*/
int __init armctrl_init(void __iomem * base, unsigned int irq_start,
u32 armctrl_sources, u32 resume_sources)
{
unsigned int irq;
for (irq = 0; irq < BCM2708_ALLOC_IRQS; irq++) {
unsigned int data = irq;
if (irq >= INTERRUPT_JPEG && irq <= INTERRUPT_ARASANSDIO)
data = remap_irqs[irq - INTERRUPT_JPEG];
irq_set_chip(irq, &armctrl_chip);
irq_set_chip_data(irq, (void *)data);
irq_set_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_DISABLED);
}
armctrl_pm_register(base, irq_start, resume_sources);
init_FIQ(FIQ_START);
return 0;
}
void __init s3c2416_init_irq(void)
{
pr_info("S3C2416: IRQ Support\n");
#ifdef CONFIG_FIQ
init_FIQ(FIQ_START);
#endif
s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2416base[0], NULL,
0x4a000000);
if (IS_ERR(s3c_intc[0])) {
pr_err("irq: could not create main interrupt controller\n");
return;
}
s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2416subint[0],
s3c_intc[0], 0x4a000018);
s3c_intc[2] = s3c24xx_init_intc(NULL, &init_s3c2416_second[0],
NULL, 0x4a000040);
}
/*
* This function initializes the AVIC hardware and disables all the
* interrupts. It registers the interrupt enable and disable functions
* to the kernel for each interrupt source.
*/
void __init mxc_init_irq(void __iomem *irqbase)
{
int i;
avic_base = irqbase;
/* put the AVIC into the reset value with
* all interrupts disabled
*/
__raw_writel(0, avic_base + AVIC_INTCNTL);
__raw_writel(0x1f, avic_base + AVIC_NIMASK);
/* disable all interrupts */
__raw_writel(0, avic_base + AVIC_INTENABLEH);
__raw_writel(0, avic_base + AVIC_INTENABLEL);
/* all IRQ no FIQ */
__raw_writel(0, avic_base + AVIC_INTTYPEH);
__raw_writel(0, avic_base + AVIC_INTTYPEL);
for (i = 0; i < MXC_INTERNAL_IRQS; i++) {
set_irq_chip(i, &mxc_avic_chip);
set_irq_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID);
}
/* Set default priority value (0) for all IRQ's */
for (i = 0; i < 8; i++)
__raw_writel(0, avic_base + AVIC_NIPRIORITY(i));
/* init architectures chained interrupt handler */
mxc_register_gpios();
#ifdef CONFIG_FIQ
/* Initialize FIQ */
init_FIQ();
#endif
printk(KERN_INFO "MXC IRQ initialized\n");
}
/*
* This function initializes the TZIC hardware and disables all the
* interrupts. It registers the interrupt enable and disable functions
* to the kernel for each interrupt source.
*/
void __init tzic_init_irq(void __iomem *irqbase)
{
int i;
tzic_base = irqbase;
/* put the TZIC into the reset value with
* all interrupts disabled
*/
i = __raw_readl(tzic_base + TZIC_INTCNTL);
__raw_writel(0x80010001, tzic_base + TZIC_INTCNTL);
__raw_writel(0x1f, tzic_base + TZIC_PRIOMASK);
__raw_writel(0x02, tzic_base + TZIC_SYNCCTRL);
for (i = 0; i < 4; i++)
__raw_writel(0xFFFFFFFF, tzic_base + TZIC_INTSEC0(i));
/* disable all interrupts */
for (i = 0; i < 4; i++)
__raw_writel(0xFFFFFFFF, tzic_base + TZIC_ENCLEAR0(i));
/* all IRQ no FIQ Warning :: No selection */
for (i = 0; i < MXC_INTERNAL_IRQS; i++) {
set_irq_chip(i, &mxc_tzic_chip.base);
set_irq_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID);
}
#ifdef CONFIG_FIQ
/* Initialize FIQ */
init_FIQ();
#endif
pr_info("TrustZone Interrupt Controller (TZIC) initialized\n");
}
