/*
* Breathe some life into the CPU...
*
* Set up the memory map,
* initialize a bunch of registers,
* initialize the UPM's
*/
void cpu_init_f(void)
{
/*
* if we come from RAM we assume the CPU is
* already initialized.
*/
#ifndef CONFIG_MONITOR_IS_IN_RAM
volatile wdog_t *wdog_reg = (wdog_t *) (MMAP_WDOG);
volatile gpio_t *gpio_reg = (gpio_t *) (MMAP_GPIO);
/* Kill watchdog so we can initialize the PLL */
wdog_reg->wcr = 0;
/* FlexBus Chipselect */
init_fbcs();
#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
#ifdef CONFIG_FSL_I2C
CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR;
CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
#endif
/* enable instruction cache now */
icache_enable();
}
/*
* Breath some life into the CPU...
*
* Set up the memory map,
* initialize a bunch of registers,
* initialize the UPM's
*/
void cpu_init_f(void)
{
/*
* NOTE: by setting the GPIO_FUNCTION registers, we ensure that the UART pins
* (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins
* which is their primary function.
* ~Jeremy
*/
mbar2_writeLong(MCFSIM_GPIO_FUNC, CONFIG_SYS_GPIO_FUNC);
mbar2_writeLong(MCFSIM_GPIO1_FUNC, CONFIG_SYS_GPIO1_FUNC);
mbar2_writeLong(MCFSIM_GPIO_EN, CONFIG_SYS_GPIO_EN);
mbar2_writeLong(MCFSIM_GPIO1_EN, CONFIG_SYS_GPIO1_EN);
mbar2_writeLong(MCFSIM_GPIO_OUT, CONFIG_SYS_GPIO_OUT);
mbar2_writeLong(MCFSIM_GPIO1_OUT, CONFIG_SYS_GPIO1_OUT);
/*
* dBug Compliance:
* You can verify these values by using dBug's 'ird'
* (Internal Register Display) command
* ~Jeremy
*
*/
mbar_writeByte(MCFSIM_MPARK, 0x30); /* 5249 Internal Core takes priority over DMA */
mbar_writeByte(MCFSIM_SYPCR, 0x00);
mbar_writeByte(MCFSIM_SWIVR, 0x0f);
mbar_writeByte(MCFSIM_SWSR, 0x00);
mbar_writeLong(MCFSIM_IMR, 0xfffffbff);
mbar_writeByte(MCFSIM_SWDICR, 0x00);
mbar_writeByte(MCFSIM_TIMER1ICR, 0x00);
mbar_writeByte(MCFSIM_TIMER2ICR, 0x88);
mbar_writeByte(MCFSIM_I2CICR, 0x00);
mbar_writeByte(MCFSIM_UART1ICR, 0x00);
mbar_writeByte(MCFSIM_UART2ICR, 0x00);
mbar_writeByte(MCFSIM_ICR6, 0x00);
mbar_writeByte(MCFSIM_ICR7, 0x00);
mbar_writeByte(MCFSIM_ICR8, 0x00);
mbar_writeByte(MCFSIM_ICR9, 0x00);
mbar_writeByte(MCFSIM_QSPIICR, 0x00);
mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */
mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); /* Enable a 1 cycle pre-drive cycle on CS1 */
/* Setup interrupt priorities for gpio7 */
/* mbar2_writeLong(MCFSIM_INTLEV5, 0x70000000); */
/* IDE Config registers */
mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020);
mbar2_writeLong(MCFSIM_IDECONFIG2, 0x00000000);
/* FlexBus Chipselect */
init_fbcs();
/* enable instruction cache now */
icache_enable();
}
void cpu_init_f(void)
{
#ifndef CONFIG_WATCHDOG
/* Disable the watchdog if we aren't using it */
mbar_writeShort(MCF_WTM_WCR, 0);
#endif
/* FlexBus Chipselect */
init_fbcs();
#ifdef CONFIG_SYS_MCF_SYNCR
/* Set clockspeed according to board header file */
mbar_writeLong(MCF_FMPLL_SYNCR, CONFIG_SYS_MCF_SYNCR);
#else
/* Set clockspeed to 100MHz */
mbar_writeLong(MCF_FMPLL_SYNCR,
MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0));
#endif
while (!mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK) ;
}
/*
* Breath some life into the CPU...
*
* Set up the memory map,
* initialize a bunch of registers,
* initialize the UPM's
*/
void cpu_init_f(void)
{
mbar_writeByte(MCFSIM_MPARK, 0x40); /* 5249 Internal Core takes priority over DMA */
mbar_writeByte(MCFSIM_SYPCR, 0x00);
mbar_writeByte(MCFSIM_SWIVR, 0x0f);
mbar_writeByte(MCFSIM_SWSR, 0x00);
mbar_writeByte(MCFSIM_SWDICR, 0x00);
mbar_writeByte(MCFSIM_TIMER1ICR, 0x00);
mbar_writeByte(MCFSIM_TIMER2ICR, 0x88);
mbar_writeByte(MCFSIM_I2CICR, 0x00);
mbar_writeByte(MCFSIM_UART1ICR, 0x00);
mbar_writeByte(MCFSIM_UART2ICR, 0x00);
mbar_writeByte(MCFSIM_ICR6, 0x00);
mbar_writeByte(MCFSIM_ICR7, 0x00);
mbar_writeByte(MCFSIM_ICR8, 0x00);
mbar_writeByte(MCFSIM_ICR9, 0x00);
mbar_writeByte(MCFSIM_QSPIICR, 0x00);
mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */
mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
/*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); */ /* Enable a 1 cycle pre-drive cycle on CS1 */
/* FlexBus Chipselect */
init_fbcs();
#ifdef CONFIG_FSL_I2C
CONFIG_SYS_I2C_PINMUX_REG =
CONFIG_SYS_I2C_PINMUX_REG & CONFIG_SYS_I2C_PINMUX_CLR;
CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
#ifdef CONFIG_SYS_I2C2_OFFSET
CONFIG_SYS_I2C2_PINMUX_REG &= CONFIG_SYS_I2C2_PINMUX_CLR;
CONFIG_SYS_I2C2_PINMUX_REG |= CONFIG_SYS_I2C2_PINMUX_SET;
#endif
#endif
/* enable instruction cache now */
icache_enable();
}
void cpu_init_f(void)
{
volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
#ifndef CONFIG_WATCHDOG
volatile wdog_t *wdg = (wdog_t *) MMAP_WDOG;
/* Disable the watchdog if we aren't using it */
wdg->cr = 0;
#endif
scm1->mpr = 0x77777777;
scm1->pacra = 0;
scm1->pacrb = 0;
scm1->pacrc = 0;
scm1->pacrd = 0;
scm1->pacre = 0;
scm1->pacrf = 0;
/* FlexBus Chipselect */
init_fbcs();
icache_enable();
}
/*
* Breath some life into the CPU...
*
* Set up the memory map,
* initialize a bunch of registers,
* initialize the UPM's
*/
void cpu_init_f(void)
{
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
#ifdef CONFIG_MCF5441x
scm_t *scm = (scm_t *) MMAP_SCM;
pm_t *pm = (pm_t *) MMAP_PM;
/* Disable Switch */
*(unsigned long *)(MMAP_L2_SW0 + 0x00000024) = 0;
/* Disable core watchdog */
out_be16(&scm->cwcr, 0);
out_8(&gpio->par_fbctl,
GPIO_PAR_FBCTL_ALE_FB_ALE | GPIO_PAR_FBCTL_OE_FB_OE |
GPIO_PAR_FBCTL_FBCLK | GPIO_PAR_FBCTL_RW |
GPIO_PAR_FBCTL_TA_TA);
out_8(&gpio->par_be,
GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 |
GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0);
/* eDMA */
out_8(&pm->pmcr0, 17);
/* INTR0 - INTR2 */
out_8(&pm->pmcr0, 18);
out_8(&pm->pmcr0, 19);
out_8(&pm->pmcr0, 20);
/* I2C */
out_8(&pm->pmcr0, 22);
out_8(&pm->pmcr1, 4);
out_8(&pm->pmcr1, 7);
/* DTMR0 - DTMR3*/
out_8(&pm->pmcr0, 28);
out_8(&pm->pmcr0, 29);
out_8(&pm->pmcr0, 30);
out_8(&pm->pmcr0, 31);
/* PIT0 - PIT3 */
out_8(&pm->pmcr0, 32);
out_8(&pm->pmcr0, 33);
out_8(&pm->pmcr0, 34);
out_8(&pm->pmcr0, 35);
/* Edge Port */
out_8(&pm->pmcr0, 36);
out_8(&pm->pmcr0, 37);
/* USB OTG */
out_8(&pm->pmcr0, 44);
/* USB Host */
out_8(&pm->pmcr0, 45);
/* ESDHC */
out_8(&pm->pmcr0, 51);
/* ENET0 - ENET1 */
out_8(&pm->pmcr0, 53);
out_8(&pm->pmcr0, 54);
/* NAND */
out_8(&pm->pmcr0, 63);
#ifdef CONFIG_SYS_I2C_0
out_8(&gpio->par_cani2c, 0xF0);
/* I2C0 pull up */
out_be16(&gpio->pcr_b, 0x003C);
/* I2C0 max speed */
out_8(&gpio->srcr_cani2c, 0x03);
#endif
#ifdef CONFIG_SYS_I2C_2
/* I2C2 */
out_8(&gpio->par_ssi0h, 0xA0);
/* I2C2, UART7 */
out_8(&gpio->par_ssi0h, 0xA8);
/* UART7 */
out_8(&gpio->par_ssi0l, 0x2);
/* UART8, UART9 */
out_8(&gpio->par_cani2c, 0xAA);
/* UART4, UART0 */
out_8(&gpio->par_uart0, 0xAF);
/* UART5, UART1 */
out_8(&gpio->par_uart1, 0xAF);
/* UART6, UART2 */
out_8(&gpio->par_uart2, 0xAF);
/* I2C2 pull up */
out_be16(&gpio->pcr_h, 0xF000);
#endif
#ifdef CONFIG_SYS_I2C_5
/* I2C5 */
out_8(&gpio->par_uart1, 0x0A);
/* I2C5 pull up */
out_be16(&gpio->pcr_e, 0x0003);
out_be16(&gpio->pcr_f, 0xC000);
#endif
/* Lowest slew rate for UART0,1,2 */
out_8(&gpio->srcr_uart, 0x00);
#endif /* CONFIG_MCF5441x */
#ifdef CONFIG_MCF5445x
scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
out_be32(&scm1->mpr, 0x77777777);
out_be32(&scm1->pacra, 0);
out_be32(&scm1->pacrb, 0);
out_be32(&scm1->pacrc, 0);
out_be32(&scm1->pacrd, 0);
out_be32(&scm1->pacre, 0);
out_be32(&scm1->pacrf, 0);
out_be32(&scm1->pacrg, 0);
/* FlexBus */
out_8(&gpio->par_be,
GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 |
GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0);
out_8(&gpio->par_fbctl,
GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA |
GPIO_PAR_FBCTL_RW_RW | GPIO_PAR_FBCTL_TS_TS);
#ifdef CONFIG_SYS_FSL_I2C
out_be16(&gpio->par_feci2c,
GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA);
#endif
#endif /* CONFIG_MCF5445x */
/* FlexBus Chipselect */
init_fbcs();
/*
* now the flash base address is no longer at 0 (Newer ColdFire family
* boot at address 0 instead of 0xFFnn_nnnn). The vector table must
* also move to the new location.
*/
if (CONFIG_SYS_CS0_BASE != 0)
setvbr(CONFIG_SYS_CS0_BASE);
icache_enable();
}
/*
* Breath some life into the CPU...
*
* Set up the memory map,
* initialize a bunch of registers,
* initialize the UPM's
*/
void cpu_init_f(void)
{
#ifndef CONFIG_WATCHDOG
/* disable watchdog if we aren't using it */
MCFWTM_WCR = 0;
#endif
#ifndef CONFIG_MONITOR_IS_IN_RAM
/* Set speed /PLL */
MCFCLOCK_SYNCR =
MCFCLOCK_SYNCR_MFD(CONFIG_SYS_MFD) |
MCFCLOCK_SYNCR_RFD(CONFIG_SYS_RFD);
while (!(MCFCLOCK_SYNSR & MCFCLOCK_SYNSR_LOCK)) ;
MCFGPIO_PBCDPAR = 0xc0;
/* Set up the GPIO ports */
#ifdef CONFIG_SYS_PEPAR
MCFGPIO_PEPAR = CONFIG_SYS_PEPAR;
#endif
#ifdef CONFIG_SYS_PFPAR
MCFGPIO_PFPAR = CONFIG_SYS_PFPAR;
#endif
#ifdef CONFIG_SYS_PJPAR
MCFGPIO_PJPAR = CONFIG_SYS_PJPAR;
#endif
#ifdef CONFIG_SYS_PSDPAR
MCFGPIO_PSDPAR = CONFIG_SYS_PSDPAR;
#endif
#ifdef CONFIG_SYS_PASPAR
MCFGPIO_PASPAR = CONFIG_SYS_PASPAR;
#endif
#ifdef CONFIG_SYS_PEHLPAR
MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
#endif
#ifdef CONFIG_SYS_PQSPAR
MCFGPIO_PQSPAR = CONFIG_SYS_PQSPAR;
#endif
#ifdef CONFIG_SYS_PTCPAR
MCFGPIO_PTCPAR = CONFIG_SYS_PTCPAR;
#endif
#if defined(CONFIG_SYS_PORTTC)
MCFGPIO_PORTTC = CONFIG_SYS_PORTTC;
#endif
#if defined(CONFIG_SYS_DDRTC)
MCFGPIO_DDRTC = CONFIG_SYS_DDRTC;
#endif
#ifdef CONFIG_SYS_PTDPAR
MCFGPIO_PTDPAR = CONFIG_SYS_PTDPAR;
#endif
#ifdef CONFIG_SYS_PUAPAR
MCFGPIO_PUAPAR = CONFIG_SYS_PUAPAR;
#endif
#if defined(CONFIG_SYS_DDRD)
MCFGPIO_DDRD = CONFIG_SYS_DDRD;
#endif
#ifdef CONFIG_SYS_DDRUA
MCFGPIO_DDRUA = CONFIG_SYS_DDRUA;
#endif
/* FlexBus Chipselect */
init_fbcs();
#endif /* CONFIG_MONITOR_IS_IN_RAM */
/* defer enabling cache until boot (see do_go) */
/* icache_enable(); */
}
