int board_init(void) { char *env_hwconfig; u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; #ifdef CONFIG_FSL_MC_ENET u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE; #endif u32 val; init_final_memctl_regs(); val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4); env_hwconfig = getenv("hwconfig"); if (hwconfig_f("dspi", env_hwconfig) && DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8))) config_board_mux(MUX_TYPE_DSPI); else config_board_mux(MUX_TYPE_SDHC); #ifdef CONFIG_ENV_IS_NOWHERE gd->env_addr = (ulong)&default_environment[0]; #endif select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN); #ifdef CONFIG_FSL_MC_ENET /* invert AQR405 IRQ pins polarity */ out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK); #endif return 0; }
int board_init(void) { init_final_memctl_regs(); #ifdef CONFIG_ENV_IS_NOWHERE gd->env_addr = (ulong)&default_environment[0]; #endif return 0; }
int board_init(void) { init_final_memctl_regs(); #ifdef CONFIG_ENV_IS_NOWHERE gd->env_addr = (ulong)&default_environment[0]; #endif select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN); return 0; }
int board_init(void) { struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; /* * Set CCI-400 control override register to enable barrier * transaction */ out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); #ifdef CONFIG_FSL_IFC init_final_memctl_regs(); #endif #ifdef CONFIG_ENV_IS_NOWHERE gd->env_addr = (ulong)&default_environment[0]; #endif #ifdef CONFIG_LAYERSCAPE_NS_ACCESS enable_layerscape_ns_access(); #endif return 0; }