void
arm_unmask_irq(uintptr_t nb)
{
struct rt1310_intc_softc *sc = intc_softc;
uint32_t value;
value = intc_read_4(sc, RT_INTC_IECR);
value |= (1 << nb);
intc_write_4(sc, RT_INTC_IMR, value);
intc_write_4(sc, RT_INTC_IECR, value);
}
void
arm_unmask_irq(uintptr_t nb)
{
dprintf("%s: %d\n", __func__, nb);
if (IS_IRQ_BASIC(nb))
intc_write_4(INTC_ENABLE_BASIC, (1 << nb));
else if (IS_IRQ_BANK1(nb))
intc_write_4(INTC_ENABLE_BANK1, (1 << IRQ_BANK1(nb)));
else if (IS_IRQ_BANK2(nb))
intc_write_4(INTC_ENABLE_BANK2, (1 << IRQ_BANK2(nb)));
else
printf("arm_mask_irq: Invalid IRQ number: %d\n", nb);
}
static void
rt1310_intc_eoi(void *data)
{
struct rt1310_intc_softc *sc = intc_softc;
int nb = (int)data;
intc_write_4(sc, RT_INTC_ICCR, 1 << nb);
if (nb == 0) {
uint32_t value;
value = intc_read_4(sc, RT_INTC_IECR);
value &= ~(1 << nb);
intc_write_4(sc, RT_INTC_IECR, value);
intc_write_4(sc, RT_INTC_IMR, value);
}
}
static void
rt1310_enable_intr(device_t dev, struct intr_irqsrc *isrc)
{
u_int irq;
unsigned int value;
struct rt1310_intc_softc *sc;
sc = intc_softc;
irq = ((struct rt1310_irqsrc *)isrc)->ri_irq;
value = intc_read_4(sc, RT_INTC_IECR);
value |= (1 << irq);
intc_write_4(sc, RT_INTC_IMR, value);
intc_write_4(sc, RT_INTC_IECR, value);
}
void
arm_mask_irq(uintptr_t nb)
{
struct rt1310_intc_softc *sc = intc_softc;
uint32_t value;
/* Make sure that interrupt isn't active already */
rt1310_intc_eoi((void *)nb);
/* Clear bit in ER register */
value = intc_read_4(sc, RT_INTC_IECR);
value &= ~(1 << nb);
intc_write_4(sc, RT_INTC_IECR, value);
intc_write_4(sc, RT_INTC_IMR, value);
intc_write_4(sc, RT_INTC_ICCR, 1 << nb);
}
static void
rt1310_disable_intr(device_t dev, struct intr_irqsrc *isrc)
{
u_int irq;
unsigned int value;
struct rt1310_intc_softc *sc;
sc = intc_softc;
irq = ((struct rt1310_irqsrc *)isrc)->ri_irq;
/* Clear bit in ER register */
value = intc_read_4(sc, RT_INTC_IECR);
value &= ~(1 << irq);
intc_write_4(sc, RT_INTC_IECR, value);
intc_write_4(sc, RT_INTC_IMR, value);
intc_write_4(sc, RT_INTC_ICCR, 1 << irq);
}
static void
rt1310_post_filter(device_t dev, struct intr_irqsrc *isrc)
{
u_int irq;
struct rt1310_intc_softc *sc;
arm_irq_memory_barrier(0);
sc = intc_softc;
irq = ((struct rt1310_irqsrc *)isrc)->ri_irq;
intc_write_4(sc, RT_INTC_ICCR, 1 << irq);
}
static int
lpc_intc_attach(device_t dev)
{
struct lpc_intc_softc *sc = device_get_softc(dev);
int rid = 0;
if (intc_softc)
return (ENXIO);
sc->li_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
RF_ACTIVE);
if (!sc->li_res) {
device_printf(dev, "could not alloc resources\n");
return (ENXIO);
}
sc->li_bst = rman_get_bustag(sc->li_res);
sc->li_bsh = rman_get_bushandle(sc->li_res);
intc_softc = sc;
arm_post_filter = lpc_intc_eoi;
/* Clear interrupt status registers and disable all interrupts */
intc_write_4(LPC_INTC_MIC_ER, 0);
intc_write_4(LPC_INTC_SIC1_ER, 0);
intc_write_4(LPC_INTC_SIC2_ER, 0);
intc_write_4(LPC_INTC_MIC_RSR, ~0);
intc_write_4(LPC_INTC_SIC1_RSR, ~0);
intc_write_4(LPC_INTC_SIC2_RSR, ~0);
return (0);
}
static int
rt1310_intr(void *arg)
{
uint32_t irq;
struct rt1310_intc_softc *sc = arg;
irq = ffs(intc_read_4(sc, RT_INTC_IPR)) - 1;
if (intr_isrc_dispatch(&sc->ri_isrcs[irq].ri_isrc,
curthread->td_intr_frame) != 0) {
intc_write_4(sc, RT_INTC_ICCR, 1 << irq);
device_printf(sc->dev, "Stray irq %u disabled\n", irq);
}
arm_irq_memory_barrier(0);
return (FILTER_HANDLED);
}
void
arm_unmask_irq(uintptr_t nb)
{
int reg;
uint32_t value;
if (nb > 63) {
nb -= 64;
reg = LPC_INTC_SIC2_ER;
} else if (nb > 31) {
nb -= 32;
reg = LPC_INTC_SIC1_ER;
} else
reg = LPC_INTC_MIC_ER;
/* Set bit in ER register */
value = intc_read_4(reg);
value |= (1 << nb);
intc_write_4(reg, value);
}
static void
lpc_intc_eoi(void *data)
{
int reg;
int nb = (int)data;
uint32_t value;
if (nb > 63) {
nb -= 64;
reg = LPC_INTC_SIC2_RSR;
} else if (nb > 31) {
nb -= 32;
reg = LPC_INTC_SIC1_RSR;
} else
reg = LPC_INTC_MIC_RSR;
/* Set bit in RSR register */
value = intc_read_4(reg);
value |= (1 << nb);
intc_write_4(reg, value);
}
void
arm_mask_irq(uintptr_t nb)
{
int reg;
uint32_t value;
/* Make sure that interrupt isn't active already */
lpc_intc_eoi((void *)nb);
if (nb > 63) {
nb -= 64;
reg = LPC_INTC_SIC2_ER;
} else if (nb > 31) {
nb -= 32;
reg = LPC_INTC_SIC1_ER;
} else
reg = LPC_INTC_MIC_ER;
/* Clear bit in ER register */
value = intc_read_4(reg);
value &= ~(1 << nb);
intc_write_4(reg, value);
}
static int
rt1310_intc_attach(device_t dev)
{
struct rt1310_intc_softc *sc = device_get_softc(dev);
int rid = 0;
int i;
if (intc_softc)
return (ENXIO);
sc->dev = dev;
sc->ri_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
RF_ACTIVE);
if (!sc->ri_res) {
device_printf(dev, "could not alloc resources\n");
return (ENXIO);
}
sc->ri_bst = rman_get_bustag(sc->ri_res);
sc->ri_bsh = rman_get_bushandle(sc->ri_res);
intc_softc = sc;
#ifndef INTRNG
arm_post_filter = rt1310_intc_eoi;
#else
rt1310_pic_attach(sc);
#endif
intc_write_4(sc, RT_INTC_IECR, 0);
intc_write_4(sc, RT_INTC_ICCR, ~0);
for (i = 0; i <= INTC_NIRQS; ++i) {
intc_write_4(sc, RT_INTC_SCR0+i*4,
(irqdef[i].ri_trig << RT_INTC_TRIG_SHIF) |
irqdef[i].ri_prio);
intc_write_4(sc, RT_INTC_SVR0+i*4, i);
}
/* Clear interrupt status registers and disable all interrupts */
intc_write_4(sc, RT_INTC_ICCR, ~0);
intc_write_4(sc, RT_INTC_IMR, 0);
return (0);
}
static inline void
bcm_intc_isrc_unmask(struct bcm_intc_softc *sc, struct bcm_intc_irqsrc *bii)
{
intc_write_4(sc, bii->bii_enable_reg, bii->bii_mask);
}
