static void *work(void *arg)
{
struct intel_batchbuffer *batch;
render_copyfunc_t rendercopy = get_render_copyfunc(devid);
drm_intel_context *context;
drm_intel_bufmgr *bufmgr;
int thread_id = *(int *)arg;
int td_fd;
int i;
if (multiple_fds)
td_fd = fd = drm_open_any();
else
td_fd = fd;
assert(td_fd >= 0);
bufmgr = drm_intel_bufmgr_gem_init(td_fd, 4096);
batch = intel_batchbuffer_alloc(bufmgr, devid);
context = drm_intel_gem_context_create(bufmgr);
if (!context) {
returns[thread_id] = 77;
goto out;
}
for (i = 0; i < iter; i++) {
struct scratch_buf src, dst;
init_buffer(bufmgr, &src, 4096);
init_buffer(bufmgr, &dst, 4096);
if (uncontexted) {
assert(rendercopy);
rendercopy(batch, &src, 0, 0, 0, 0, &dst, 0, 0);
} else {
int ret;
ret = drm_intel_bo_subdata(batch->bo, 0, 4096, batch->buffer);
assert(ret == 0);
intel_batchbuffer_flush_with_context(batch, context);
}
}
out:
drm_intel_gem_context_destroy(context);
intel_batchbuffer_free(batch);
drm_intel_bufmgr_destroy(bufmgr);
if (multiple_fds)
close(td_fd);
pthread_exit(&returns[thread_id]);
}
void gen9_render_copyfunc(struct intel_batchbuffer *batch,
drm_intel_context *context,
struct igt_buf *src, unsigned src_x, unsigned src_y,
unsigned width, unsigned height,
struct igt_buf *dst, unsigned dst_x, unsigned dst_y)
{
uint32_t ps_sampler_state, ps_kernel_off, ps_binding_table;
uint32_t scissor_state;
uint32_t vertex_buffer;
uint32_t batch_end;
intel_batchbuffer_flush_with_context(batch, context);
batch_align(batch, 8);
batch->ptr = &batch->buffer[BATCH_STATE_SPLIT];
annotation_init(&aub_annotations);
ps_binding_table = gen8_bind_surfaces(batch, src, dst);
ps_sampler_state = gen8_create_sampler(batch);
ps_kernel_off = gen8_fill_ps(batch, ps_kernel, sizeof(ps_kernel));
vertex_buffer = gen7_fill_vertex_buffer_data(batch, src,
src_x, src_y,
dst_x, dst_y,
width, height);
cc.cc_state = gen6_create_cc_state(batch);
cc.blend_state = gen8_create_blend_state(batch);
viewport.cc_state = gen6_create_cc_viewport(batch);
viewport.sf_clip_state = gen7_create_sf_clip_viewport(batch);
scissor_state = gen6_create_scissor_rect(batch);
/* TODO: theree is other state which isn't setup */
assert(batch->ptr < &batch->buffer[4095]);
batch->ptr = batch->buffer;
/* Start emitting the commands. The order roughly follows the mesa blorp
* order */
OUT_BATCH(GEN6_PIPELINE_SELECT | PIPELINE_SELECT_3D |
GEN9_PIPELINE_SELECTION_MASK);
gen8_emit_sip(batch);
gen7_emit_push_constants(batch);
gen9_emit_state_base_address(batch);
OUT_BATCH(GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC);
OUT_BATCH(viewport.cc_state);
OUT_BATCH(GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP);
OUT_BATCH(viewport.sf_clip_state);
gen7_emit_urb(batch);
gen8_emit_cc(batch);
gen8_emit_multisample(batch);
gen8_emit_null_state(batch);
OUT_BATCH(GEN7_3DSTATE_STREAMOUT | (5 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
gen7_emit_clip(batch);
gen8_emit_sf(batch);
gen8_emit_ps(batch, ps_kernel_off);
OUT_BATCH(GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS);
OUT_BATCH(ps_binding_table);
OUT_BATCH(GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS);
OUT_BATCH(ps_sampler_state);
OUT_BATCH(GEN6_3DSTATE_SCISSOR_STATE_POINTERS);
OUT_BATCH(scissor_state);
gen9_emit_depth(batch);
gen7_emit_clear(batch);
gen6_emit_drawing_rectangle(batch, dst);
gen7_emit_vertex_buffer(batch, vertex_buffer);
gen6_emit_vertex_elements(batch);
gen8_emit_vf_topology(batch);
gen8_emit_primitive(batch, vertex_buffer);
OUT_BATCH(MI_BATCH_BUFFER_END);
batch_end = batch_align(batch, 8);
assert(batch_end < BATCH_STATE_SPLIT);
annotation_add_batch(&aub_annotations, batch_end);
dump_batch(batch);
annotation_flush(&aub_annotations, batch);
gen6_render_flush(batch, context, batch_end);
intel_batchbuffer_reset(batch);
}
